On-Chip Power Distribution Networks Get Help from Magwel’s RNi

Counting squares is a useful tool for calculating simple resistance in wires, but falls short in reality when wires deviate from ideal. Frequently the use of RC extraction tools for determining resistance in signal lines in digital designs can be effective and straightforward. However, there are classes of nets in designs that confound extraction tools. Good examples of these are found in power distribution networks. Also, nets found in memory designs are excellent candidates for deeper analysis.

At one end of the spectrum of solutions we find full wave solvers. While they are the most accurate method for analysis of electrical properties in all kinds of metal structures, they are troublesome to apply to complex on chip metal structures. Full wave solvers are difficult to set up, run slowly and output S-parameters, which are vexing to use for subsequent interpretation. Consequently, use of full wave solvers is often limited to analysis of on-chip inductors and capacitors.

The output of RC extractors fall short when complex nets are involved. A typical power or ground net may have thousands or more end points. What matters to the design is the actual resistance at each of these end points. To further complicate solving this problem these nets are often highly interconnected to themselves. The best example of this is a mesh style power or ground net. There are many parallel current paths in these nets, which can greatly complicate the effective resistance between any two points on the network.

Fortunately for designers who need to tune and optimize endpoint resistances in large complex nets, such as power distribution networks, there is an easy to use solution available from Magwel. Their Resistance Network Integrity (RNi) tool provides an intuitive and easy to use approach that provides comprehensive analysis and an interactive interface for finding high resistance segments and endpoints.

Magwel’s RNi uses solver technology that can handle complex interconnect without the difficult set up typically required for other solvers. RNi reads in the layout in GDS and allows the user to select a pad or create a contact point to use as a reference point for the resistance calculation. The RNi technology file comes from information found in foundry supplied ITF files. Once the solver is started, results are available quickly.

The solver extracts the entire net, including vias and metal on all layers. Another benefit is that no stimulus is needed and the design does not have to be LVS clean. It is extremely valuable to be able to plan power distribution networks as early as possible in the design cycle.

RNi calculates the total resistance to all points on the selected net from the contact point or pad that was set at the beginning of the run. It’s easiest to view the results in the tool’s field view. This is a graphical view that uses color to visualize the resistance values. Also, moving the mouse over any point in the net will display the resistance value to that point as a number. Of course, in a large chip, finding a high resistance point can be like finding a needle in a haystack. RNi will quickly list the top values and allows the user to zoom in on the view each of them with a single click on the mouse.

RNi is a natural addition to Magwel’s product line up. Accurate resistance extraction is an absolute necessity for ESD induced voltage drop during discharge events. Magwel is applying its solver based resistance extraction to this problem in its ESDi product. The same technology comes into play during power device gate, source and drain network simulation and analysis in their PTM product family. For more information on Magwel and their solutions for improving design efficiency, reducing power, and increasing reliability, refer to their website here.