Ensuring ESD Integrity

Electro Static Discharge (ESD) is a fact of life for IC designs and has been ever since electronics were first created and then started failing because of sudden, large currents flowing through the design caused by human, processing or machine contact. It’s just too expensive to layout an IC today, fabricate it, test for ESD compliance, and then iterate when the layout fails. Fortunately for us, EDA vendors have developed tools that are able to analyze an IC layout for ESD compliance prior to tape out that can:

• Find missing or under-sized vias
• Detect curent crowding in metal layers and vias
• Pinpoint excessive bus resistance that can lead to voltage stress over protected devices
• Flag wrong or missing ESD protection devices
• Calculate ESD device burnout
• Simulate if a protected device has reached burnout
• Report if oxide breakdown is being caused by voltage stress
• Alert if a protected device triggers before a parallel ESD device
• Shows if there’s an imbalanced current distribution over the fingers of an ESD device

One vendor that I talked with at DACthis year was Magwel, and I recently had a chance to get an update on their new EDA tool for ESD analysis called ESDi. This tool runs on the chip-level IC layout by extracting a netlist with layout parasitics, and running a simulation-based ESD verification. The static simulations use both the Human Body Model (HBM) and the Machine Model (MM) on all of the pad-to-pad combinations:

Human Body Model (HBM)

Machine Model (MM)

There’s another ESD model called the Charged Device Model (CDM) that is planned for introduction later in the year, so stay tuned for that.

Charged Device Model (CDM)

For each specific IC technology there are Transmission Line Pulse (TLP) techniques used to create table models for ESD events, so you don’t have to do your own modeling. Your IC design can contain multiple power domains and the pads can be grouped. During ESD simulation the currents inside of each ESD cell are calculated, so that you can read reports on things like:

• Bus resistances
• Voltage stress in core circuits
• Electro-migration violations
• Device burnout

Extracting a netlist for all of the power and ground nets is computationally challenging, so the ESDi tool uses multi-threading to help deliver results in a reasonable amount of time.

Current Density Report

The actual path that an ESD discharge event may travel inside of an IC is kind of tricky thing to uncover, so this tool is smart enough to trace multiple, parallel paths which include parasitic Bipolar devices, self-protecting devices, plus stacked or parallel ESD devices:

ESD Path Tracing

To be thorough, ESDi will automatically find and then simulate all current paths using the TLP models. Triggering of multiple parallel power clamps is accurately simulated in ESDi taking into account IR-drops in path resistances and trigger voltages. Some competing tools assume that only 1 power clamp will be triggered at any given time, which often leads to overestimation of path resistances and false positives. The latter need to be manually checked and possibly waved, which is a time consuming and error-prone process.

You can also have different ESD specifications used for each test run. The GUI helps make it easy to learn the tool for both viewing results plus design debug tasks.

Actual ESD tool results from a mixed-signal FPGA chip IO ring using 83 pads designed in a 40nm technology show just how fast the ESD analysis is:

• Extract a netlist from layout in 10 minutes
• Run 4,160 HBM tests and Electro-Migration tests in 30 minutes
• Using 4 threads on an i7 processor with 8GB of RAM

A mixed-signal FPGA chip, IO ring

You can now analyze your IC layout for ESD compliance prior to tape out and know that it will pass HBM and MM testing by using an EDA tool like ESDi from Magwel. This approach will eliminate silicon re-spins and keep your customers happy because they won’t be returning failed parts.