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Challenges in 3D-IC and 2½D Design

Challenges in 3D-IC and 2½D Design
by Paul McLellan on 12-09-2011 at 5:18 pm

 3D IC design and what has come to be known as 2½D IC design, with active die on a silicon interposer, require new approaches to verification since the through silicon vias (TSVs) and the fact that several different semiconductor processes may be involved create a new set of design challenges

The power delivery network is a challenge in a modern 2D (i.e. normal) die but designing the power delivery network is more challenging still with TSVs, passing the power up from the die at the bottom of the stack (or the interposer) up to the higher die. There are possibilities of inter-die noise and other issues. There are two approaches to handle this. The first approach, which can be used if all the die data is available, is to simulated everything concurrently. The second approach is to use models where a chip power model (CPM) is generated for missing data for co-analysis with the available data.

Another specific power-related problem is thermal and thermal-induced stress failures. The IC power is very temperature-dependent, especially leakage power. In a 3D design the thermal dissipation is more complex. Similar to CPM, a chip thermal model (CTM) can be generated for each die in the design, including temperature dependent power and per-layer metal density. The CTM is used for accurate prediction of power and temperature distribution.

From a signal integrity point of view, a new problem is jitter noise analysis for wide-I/O applications. In an interposer design, which is a lot less pin limited than a regular package, a parallel bus might have as many as 8K bits which, apart from skew considerations, can introduce significant jitter due to simultaneous switching.

So it is clear that a new approach is required, a comprehensive anaysis for power, noise, and reliability to ensure successful tape-out of 3D and silicon-interposer-based designs.

This is a summary of a paper by Dr Norman Chang of Apache presented at the IEEE/CPMT society 3D-IC workshop held in Newport Beach on December 9th. The conference website is here.

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