Achieving a Predictable SignOff in 7nm

Designing with advanced-nodes FinFETs such as 7nm node involves a more complex process than prior nodes. As secondary physical effects are no longer negligible, the traditional margin-based approach applied at various design abstraction levels is considered ineffective. Coupled with the increase of device counts, failing to account for all of these effects will add design risks including impact to yield and PPA (Power, Performance and Area).

Variability and Margin
Without proper analytics, the physical effects generally accounted for as variability in many forms (voltage drop, temperature, process) and its manifestations such as timing uncertainties, margin, derating, etc., pose significant challenges to the design closure. The grid complexity in 7nm designs (with power grids in the order of 10B+ nodes) has increased and the use of ultra-low voltage supply has also compressed margin and worsened variability, demanding an increase in scenario coverage to ensure voltage and timing closures.
Furthermore, the variability increase also complicates predicting true silicon behavior, which is critically needed for a successful product ramp process.

In the Ansys Webinar titled “Addressing Multiphysics Challenges in 7nm FinFET Designs”, a holistic approach in addressing these challenges was presented. It started with the understanding of how the design fits within the process space and what types of subjected scenarios that could lead to potential design risks.

Power Integrity and Thermal
At the epicenter of these challenges is power, a critical source to each device operation on the silicon. Power distribution network (PDN) integrity drives switching activities and is prone to imbalances that could induce undesired surprises such as IR drop issues. For example, poor bump and RDL design could contribute to poor on-chip device operation or even failure at silicon bring-up.

As expected, the initial objective is to identify potential hotspot localities and fix these vulnerabilities early during the design implementation cycle. Consequently, an accurate way of quantifying the interacting physics is needed. For example, the analytics tool such as Ansys’ RedHawk helps identify an IR drop caused by packaging or design activity, and provide data points for corrective remedies.

In a wider context, assessing power integrity in the design flow starts at the power planning stage, in which grid quality is analyzed through BQM (Build Quality Metrics) approach. During the subsequent block-level build and PDN optimization, multiple reliability analysis such as static/dynamic voltage drops and signal EM (EMIR) are done. Structural grid checks are then applied to locate potential issues. Given that it is easier to put out a fire on a few trees than fighting a forest fire, fixing localized design issues early helps to contain smaller problems from getting out-of-hand. For example, taking care of the outliers in the generated histogram from analytics data can reduce the number of critical issues into a manageable list.

Aside from power, thermal is also another critical factor. The heat generation, dissipation flow and thermal couplings of chip components versus any optical components in a heterogeneous 3D-IC could impact the overall chip power or performance. Localized activities and PVT conditions also influence the device aging process.

Multivariable and Predictive Signoff
The key to tackling multiphysics challenges is to infuse analytics into the existing solution such as in power integrity methodology in such as a way that it enables a predictive signoff quality. The traditional analysis flow utilizing both vector and vectorless simulation approach has challenges, as it relies on a set of correct scenarios selection. For example, many modern designs have application dependencies that may uniquely translate to different activities sequences at the core level. Therefore, to arrive at a set of vectors that provide good coverage of activities is hard.
As the impact of multiphysics interactions are eventually measured in term of performance design metric (timing), it is necessary to facilitate feeding back the various simulation generated data points into the overall design closure flow. Ansys’ Path FX platform fills the gap between SPICE level circuit simulation and static timing analysis. It provides context-aware multiphysics timing analysis and complements the mainstream design flows by retaining the performance, capacity and usability of timing analysis engine.

Path FX target use models include to complement existing STA by validating at risk paths at each design iteration, identify safe slack and add additional guardband to at-risk paths not covered by margins. It is also capable of fine-tuning the process models for better correlation with silicon and use them to further identify at-risk paths. On a 7nm testcase, it delivers an accuracy within 2% versus SPICE simulation result. Path-FX has also been integrated with RedHawk-SC to address voltage drop impact assessment on timing. With Ansys’ SeaScape architecture it enables design teams to leverage big data analytics to handle the data demands of multiphysics chip-package-board simulation and testing.

In summary, 7nm designs are subject to a more complex multi-physics environment. Successful silicon tapeout and bring up require addressing their impacts on delay variability, validating at-risk areas on silicon and proper use of safe guardband.

To view this on-demand Webinar on how Ansys multiphysics simulations can address the different forms of variability and their impact on performance, please check HERE.