Check this webinar out – Mediatek will share a novel approach to early IR drop estimation. Competition in system design has become even more intense because potential markets are huge and there are more players with deep pockets chasing those markets. Wherever you are in those value chains, you want to shift everything left to accelerate schedules. But there’s a challenge in that goal; what do you do if the step you want to accelerate depends on simulation vectors? Dynamic IR signoff is one such application.
REGISTER HERE for this webinar on October 2[SUP]nd[/SUP], 2018 at 9am PDT.
You could wait until late in design but then you take the risk that you’ll find a significant weakness when you’re almost out of time. If you start early, you can use a vectorless approach, but the general view has been that these are too inaccurate to provide effective guidance. Necessity (or at least competition) apparently is the mother of invention. MediaTek will share in this webinar how they use a vectorless approach to get to very high IR coverage, isolate hotspots and increase confidence in their final signoff.
REGISTER HERE for this webinar on October 2[SUP]nd[/SUP], 2018 at 9am PDT.
Summary
Next-generation mobile, automotive and networking applications require the use of advanced SoCs to deliver greater functionality and higher performance at much lower power. For these SoCs, the margins are smaller, schedules are tighter while costs are higher. Faster convergence with exhaustive coverage is therefore imperative for first time silicon success. For next generation applications, the numbers of vectors for which you need to run simulations have increased multi-fold. It is nearly impossible to uncover potential design weaknesses when you are simulating a handful of vectors for just a fraction of second. How do you ensure you have enough design coverage? The common approach for dynamic IR signoff uses vector-patterns with true delay information. This approach is performed late in the design cycle, requires long simulation time and yields limited IR coverage due to limited vector-patterns. Published traditional vectorless approaches produce unsatisfactory IR coverage and correlation to vector-patterns. Attend this webinar to learn how MediaTek’s novel multicycle vectorless flow uses a design power target, selectively sets a high toggle rate and enables state-propagation features in ANSYS-RedHawk. The new flow achieves 97 percent IR coverage of non-memory cells and 100 percent IR coverage of memory cells, captures IR hotspots and reduces run time by 3X, accelerating signoff processes and improving power grid quality.
Speakers
Annapoorna Krishnaswamy, Product Marketing Manager at ANSYS
Huajun Wen is a distinguished engineer at Mediatek. She is currently responsible for developing new IR signoff flows to ensure robust and efficient power grid designs of Mediatek products. She has comprehensive knowledge and expertise in modeling and reducing IR from PMIC to transistors. Her experiences span chip power modeling and characterization, physical design and timing methodology, and on-chip power conversion techniques. Prior to joining Mediatek at 2013, Huajun was an IBM Senior Technical Staff Member, holding various physical design leadership positions on IBM Power and Mainframe processors designs as well as Cell Processor design used in the Sony Playstation3. She published 20+ technical papers and holds 10+ US granted patents. Huajun received her Ph.D. in solid state physics from Free University Berlin, Germany.
About ANSYS
If you’ve ever seen a rocket launch, flown on an airplane, driven a car, used a computer, touched a mobile device, crossed a bridge, or put on wearable technology, chances are you’ve used a product where ANSYS software played a critical role in its creation. ANSYS is the global leader in engineering simulation. We help the world’s most innovative companies deliver radically better products to their customers. By offering the best and broadest portfolio of engineering simulation software, we help them solve the most complex design challenges and engineer products limited only by imagination.
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