WP_Term Object
(
    [term_id] => 34
    [name] => ANSYS, Inc.
    [slug] => ansys-inc
    [term_group] => 0
    [term_taxonomy_id] => 34
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 191
    [filter] => raw
    [cat_ID] => 34
    [category_count] => 191
    [category_description] => 
    [cat_name] => ANSYS, Inc.
    [category_nicename] => ansys-inc
    [category_parent] => 157
)
            
Ansys IDEAS Digital Forum Banner
WP_Term Object
(
    [term_id] => 34
    [name] => ANSYS, Inc.
    [slug] => ansys-inc
    [term_group] => 0
    [term_taxonomy_id] => 34
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 191
    [filter] => raw
    [cat_ID] => 34
    [category_count] => 191
    [category_description] => 
    [cat_name] => ANSYS, Inc.
    [category_nicename] => ansys-inc
    [category_parent] => 157
)

Webinar: IP integration methodology

Webinar: IP integration methodology
by Paul McLellan on 07-17-2011 at 12:24 pm

 The next Apache webinar is coming up on 21st July at 11am Pacific time on “IP integration methodology”.

This webinar will be conducted by Arvind Shanmugavel, Director Applications Engineering at Apache Design Solutions. Mr. Shanmugavel has been with Apache since 2007, supporting the RedHawk and Totem product lines. Prior to Apache he worked at Sun Microsystems for several years, leading various design initiatives for advanced microprocessor designs. He received his Masters in Electrical Engineering from the University of Cincinnati, Ohio.

Today’s SoC consists of several IP blocks, developed internally or externally. To achieve a successful integration of IP into a single chip design requires a methodology that considers the power noise impact of merging sensitive analog circuitry with high-speed digital logic on the same piece of silicon. In addition, it must handle the sharing of IP information and knowledge between disparate design groups to ensure the design will work to specification and at the lowest cost. Apache’s power analysis and optimization solutions allow IP designers to validate their design and create protected and portable models that can be used for mixed-signal analysis and SoC sign-off. Apache’s IP Integration Methodology targets the design, validation, and cost reduction of highly integrated mixed-signal SoCs to help deliver robust single chip designs.

More details on the webinars here.

Register to attend here (and don’t forget to select semiwiki.com in the “How did you hear about it?” box).


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