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ESD has historically been a big problem analyzed with ad-hoc approaches. As explained earlier, this is no longer an adequate way to plan nor signoff ESD protection.
Pathfinder is the first full-chip comprehensive ESD planning and verification solution. It is targeted to address limitations in today’s methodologies. Using a full-chip modeling approach, it can verify that a design meets ESD guidelines and identify vulnerable areas of the design. It can report if current density exceeds limits for wires and vias. It works for both digital and analog circuits.
There are three different types of analysis.
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First, human body model (HBM) and machine model (MM) checks. These are the ESD problems that can result from either humans touching the pins or during manufacturing test and assembly. Pathfinder will check to ensure than if ESD voltage occurs between any two pins (or bumps) then it will traverse one or more clamp cells placed between those pins. First the loop resistance through each clamp cell is estimated. If the resistance is too high then that clamp cell is ignored and only any remaining cells (if any) for that path are considered. Checks are performed to ensure that the ESD protection is sufficient between each pair of pins.
Charged device model (CDM) checks. This is check for build up in logic, package capacitors and other circuits such as memories that need to have low resistance discharge paths.
Current density checks. This involve estimating the current density in wires following the injection of current into any pin pair. It calculates the current through the wires and vias and highlights any which fail the current density limits (as defined by the process guidelines).
Following this analysis, extensive information can be created to enable debugging: reports, histograms and graphical displays overlaid onto the layout. This makes it easy to perform what-if experiments without leaving the tool. Once any changes are confirmed, an ECO report is created to allow for implementation of those changes in the final layout of the chip.
Pathfinder is used in two different ways. Early in the design it can be used for ESD planning, especially on bumped chips which need to contain extensive ESD protection circuitry in the core and not just in an IO ring. If this is not done, and ESD protection circuitry is only added very late in the design process, it risks causing unexpected area (and perhaps timing) problems and thus potentially major schedule impact. The second way is to analyze the final design to signoff on the ESD protection prior to tapeout.
ESD has historically been a big problem analyzed with ad-hoc approaches. As explained earlier, this is no longer an adequate way to plan nor signoff ESD protection.
Following this analysis, extensive information can be created to enable debugging: reports, histograms and graphical displays overlaid onto the layout. This makes it easy to perform what-if experiments without leaving the tool. Once any changes are confirmed, an ECO report is created to allow for implementation of those changes in the final layout of the chip.
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