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Will your next SoC fail because of power noise integrity in IP blocks?

Will your next SoC fail because of power noise integrity in IP blocks?
by Daniel Payne on 04-14-2015 at 5:00 pm

By the time that your SoC comes back from the fab and you plugin it into a socket on a board for testing, it’s a little late in the cycle to start thinking about reliability concerns like: dynamic voltage drop, noise coupling, EM (Electro-Migration), self-heating, thermal analysis and ESD (Electro-Static Discharge). They say that an ounce of prevention is worth a pound of cure, and that maxim is quite true when it comes to power noise integrity issues for our SoC designs filled up with re-used IP blocks and subsystems.

You could take a detailed, transistor-level approach of using a SPICE circuit simulator during the design and layout phases to measure the effects of power integrity, except that would mean you have to wait until your design has a clean LVS netlist and all of the IC layout is completed, which is just too late during the design cycle. There is a more elegant approach that uses reliability analysis throughout the entire design process, and ANSYS is one EDA vendor with tools and years of experience in this domain.

Early Grid Weakness Analysis

As soon as your IP block has a GDS II layout, then you can run an early Power and Ground (PG) grid analysis to help pinpoint any areas of the IC layout that have excessive resistance and high current drive. Feedback from this analysis allows the layout designer to start fixing the PG grid at the earliest point in the design.

IP Power Integrity Sign-off Coverage

Static IR Drop Analysis
As an IP block is powered up current starts to flow in the network, eventually reaching power and ground nets. The resistance of the PG nets multiplied by the current flowing creates a voltage drop, as ohms law states: V = I*R. When VDD levels lower, so does the noise margin, so it’s important to analyze each IP block with a static IR drop analysis, then inspect the grid for any hotspots identified, fixing the issue by adding vias, contacts or widening PG nets to lower the resistance.

Dynamic Voltage Drop Analysis
The static IR drop analysis doesn’t take into account any of the dynamic switching nature of all circuits, so a dynamic voltage drop analysis adds further reliability coverage under switching conditions. Feedback from such an analysis helps the designer to add or even reduce metal straps, vias, contacts and interconnect widths.

Related – Noise & Reliability of FinFET Designs Need Smart & Proven Methodologies – Success Stories

Substrate Noise Analysis
Digital circuits that switch simultaneously can actually inject currents into the substrate, affecting the electrical performance of nearby, sensitive analog circuits, creating computational errors and degrading performance. With substrate noise analysis you can get an idea of where the noise is coming from, and how effective your layout isolation techniques are. Running this type of analysis during assembly of IP blocks will ensure that each AMS block is well isolated from noise sources.

Related – How Early Do You Analyze Substrate Noise in SoC Design?

EM Analysis
There is a type of failure in aluminum or copper interconnect where the current density becomes so great that the atomic structure of the interconnect becomes altered enough to literally thin or narrow the interconnect, thereby greatly increasing the resistance and reliability of the interconnect. An increased current in the interconnect causes localized heating. With EM analysis the designer can see if their IP is over-design or under-designed for these high current effects. Both PG and signal interconnect should be run through EM analysis throughout the design process.

EM Sign-off Flow

Thermal Analysis

With new transistor technology like FinFET the current drive is higher than planar devices per unit area which quickly leads to an increased thermal impact, even wires and vias can fail under high temperatures after enough cycles. You will want a thermal analysis tool capable of computing the actual thermal gradient on each IP block and then recalculate EM limits on the wires and vias.

Thermal Integrity Coverage

Related – FinFET Designs Need Early Reliability Analysis

ESD Analysis
It used to be that just IO pads needed ESD protection and analysis, however at the 65 nm and lower nodes our IP blocks need ESD checks to avert device breakdown, signals melting and cross-domain issues. DRC checks are no longer sufficient for ESD analysis, so a simulation-based approach is more thorough and trusted. The physical factors that require ESD analysis are increased resistance for interconnect, higher current densities and decreased oxide thickness for transistors.

ESD Integrity Coverage

Related – SoCs More Vulnerable to ESD at Lower Nodes – Must Resolve

The specific EDA tools offered by ANSYS to help you handle power noise integrity are called RedHawkand Totem:

IP sign-off for power noise integrity

By running these analysis tools on each IP block, during chip assembly and before tape-out, you can validate that your SoC will work when it comes back from the fab.

IP Integration Validation at SoC Level


Power noise integrity is important to the reliable operation of your IP-based SoC designs, and by using the methodology described it will ensure that your next project works to spec without surprises.

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