There is a new book out from Springer. The subtitle is actually a better description that the title. The subtitle is A Practical Guide to Synopsys Design Constraints (SDC) but the title isConstraining Designs for Synthesis and Timing Analysis. The authors are Sridhar Gangadharan of Atrenta in San Jose and Sanjay Churiwala of Xilinx in Hyderabad. The final chapter on Xilinx extensions to SDC was written by Frederic Revenu (not suprisingly, from Xilinx). Given the backgrounds of the authors, the book is equally applicable to SoC/ASIC designs and to FPGA-based designs.
As a totally off-topic aside I have actually been to Hyderabad several times. At Compass I set up a remote development group with a company called CMC (now part of Tata), which was originally set up to service IBM installations after IBM India was kinda nationalized in the 1970s. The weather is great at some times of year but at other times of year it is insanely hot.
The book is, as it says on the cover, a hands-on guide to timing constraints in integrated circuit design. You will learn to maximize performance of IC designs by specifying timing requirements correctly all within the context of SDC, which is, of course, the de facto standard format for specifying constraints. The book:
- Provides a hands-on guide to create constraints for synthesis and static timing analysis (STA), using SDC
- Explains fundamental concepts around SDC constraints and its application in a design
- Explains SDC command syntax, semantics and options
- Includes key topics of interest to a synthesis, static timing or place & route engineer
- Explains which constraints command to use for ease of maintenance and reuse, given that there are often several options possible to achieve the same effect on timing
The chapters in the book are:
[LIST=1]
A complete contents listing including all the subheadings is available as a pdf.
As you can see from the chapter titles the book is pretty comprehensive and has a practical emphasis on giving the practicing engineer the knowledge to do a better job. ASIC and FPGA design flows have a heavy focus on verifying the functionality of the RTL. However, an equal emphasis on validating the timing constraints has been missing. Constraint issues can cause unpredictable design schedule, increase iteration between logical and physical design and result in late stage ECOs. The quality of the constraints has a direct relationship to the quality of the silicon. This book is has been written to address this.
Unfortunately the book is priced like a textbook with a limited audience, which of course it is. The list price from Springer is $119but Amazon has it for $99.82or you can get on Kindle for only a little less at $89.99.There is a free sample of chapter 2 available as a pdf.
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