Aveek Sarkar presented a webinar on chip-package-system (CPS) earlier this summer. One of the big challenges with low-power electronic systems is that the performance, power and price goals are mutually conflicting. It’s like the old joke about “pick any 2”. But for a real system all need to be optimized. The key, in fact, is to design everything together so as to avoid high costs that come from over-designing one particular piece, or the failure that results from under-design. Power noise, signal integrity, electromagnetic interference (EMI), thermal: all of these need to be, like Goldilock’s porridge, just right. Under control without being over-designed at high cost.
Designing the chip, package and board separately and then only bringing them together at the end is no longer adequate since there isn’t enough margin to do a reasonable job of optimizing each aspect separately. They need to be co-designed and analyzed together. Otherwise choices that seem reasonable in isolation, such as using a cheap board or cutting back on decoupling capacitors can be disastrous for system performance or reliability.
Chips are obviously very complex and it is not usually feasible to use the actual design during CPS analysis. Instead, a chip power model (CPM) is used. This captures the essential aspects of the chip to enable analysis of the chip inside its package on the board. The webinar also covers aspects of 3D design, including thermal analysis of a die stack.
The webinar provides an overview of system-aware chip design and chip-aware system design methodologies and how they address complex power, signal integrity, thermal and EMI design requirements. The webinar is now available on-demand.
The webinar registration page is here.Share this post via: