3 in 1 Hardware Verification

Aldec has offered front-end EDA tools for over 30 years but may not be a familiar name to mainstream IC design engineers. That’s probably because for most that period they haven’t really targeted IC design. They have been much more focused on PC-based design for FPGAs particularly where requirements traceability has been important, for example in avionics design, where DO-254 compliance is mandatory.

But there have been important shifts in interesting markets over the past few years which move closer to Aldec’s center of gravity. Fragmenting market needs demand device volumes that are not cost-effective in custom IC implementations, a problem further compounded by rapidly evolving standards, such as communications protocols. This drives a trend to FPGAs at higher unit costs but much lower total cost. Additionally, standards which are either regulatory or de-facto regulatory have become more important in rapidly-growing markets like automotive (ISO 26262), industrial (IEC-61508) and medical (IEC-60601).

You may be even more surprised to hear that Aldec has a prototyping/emulation product. Why would their customers need such a thing? Because FPGA/multi-FPGA designs are getting to be too big and too software-driven for burn-and-churn debug to be practical. Just as FPGA designers are turning to UVM and formal proving, they’re also turning to hardware help in verification. That’s where the latest HES release, based on Xilinx UltraScale devices, becomes interesting.

One HES7XUS1320BPX board (pictured at the beginning of this piece) containing three XCVU440 devices on a single PCB has an estimated capacity of 79 Million ASIC gates. For larger designs the system can be scaled up with a standards-based backplane that can interconnect up to four boards to provide capacity of 316 Million ASIC gates. What’s more it can be used as an emulator or an emulation slave to a master simulation.

Of course hardware alone doesn’t make an emulator. Part of what you need is reasonable setup times. Judging by comments on earlier generations it seems this is why Aldec went with the biggest Xilinx devices – to reduce the need for partitioning for many of the designs they target. But to echo a comment in a reference below, it is less obvious how well this scales if you need to go to 2 or more boards.

The other thing you need is fine-grained debug support. HES offers up to 16 groups of 16kbits of “static probes”, spread across all FPGAs in the system. These seem to be effectively instrumented into a multi-chip logic analyzer. They also offer something called dynamic probes which you can select during runtime, allowing for debug access anywhere, though at slower speeds with Xilinx readback. You also get a backdoor interface for read and write of memory.

Aldec also provides support for using emulation mode in ICE (in-circuit emulation) modeling, with support for speed bridges, as a simulation accelerator, for co-emulation with virtual models and for software debug. Apparently a pretty comprehensive solution though to dig deeper you’ll need to talk to your local distributor.

One last thing. It’s always tricky to get information on pricing but I did find this reference which suggests that in 2012, HES-7 was under $20k for a single board solution. That is a very different price range from mainstream emulation and prototyping solutions. I can’t answer to how HES could address your needs, but pricing alone should pique your interest. You can read more about the latest Aldec HES capabilities HERE. There’s also a somewhat more detailed report on HES HERE.

More articles by Bernard…