As a 30+ year semiconductor veteran I can tell you with 100% certainty that start-ups are the lifeblood of EDA. The mantra is “Innovate or Die!” and that is exactly what Defacto is doing. After more than 10 years of innovating in Design for Test at RTL, Defacto is now offering a complete EDA solution based on generic EDA tools to cover advanced Design Restructuring, Design Verification, Low Power Design, IP Integration, and RTL Signoff.
The development of Defacto’s technology began at the National Polytechnic Institute of Grenoble (INPG-France) in 1997, under the leadership of Chouki Aktouf, PhD. More than 18 man-years of work were invested in Defacto’s unique DFT technology. Dr. Aktouf and his team did the early market assessment and established proof of concept by working with a large European semiconductor manufacturer to validate the benefits of the company’s technology.
In 2003, Dr. Aktouf, Michel Oger, Philippe Duchene, and James Girand founded Defacto and the company raised Series A to D from two major investors in France, Innovacom and CIC-CM.
What does Defacto do?
Defacto provides RTL design solutions which help users to build a unified design flow where different standards like RTL for design description, UPF for power intent, SDC for timing constraints, LEF/DEF for physical design information, are considered jointly
What are the challenges facing EDA companies today?
Main challenges are three fold, first, different mergers between major semiconductor companies.
Second challenges are the new opportunities around design solutions especially for killing apps like for automotive, IOT (Internet of Things) and the ability to provide compelling solutions.
Last but not least are the emerging FPGA based solutions for complex designs, where EDA offers are still very limited compared to ASICs.
But why partitioning at RTL?
Partitioning and re-architecturing complex SoCs during or after logic synthesis is just unrealistic, knowing the complexity of the today chips with the related runtime and performance in general. So partitioning at RTL means analyzing different configurations, different scenarios, given several criteria: power, DFT, reliability, timing, physical information, etc. It’s just the way to go.
You spoke about unified flow what are the benefits to have this kind of platform?With the Defacto-based unified flow, RTL designers for example not expert in low power designs or timing will be able to automatically update the related databases UPF or SDC respectively when RTL change. Imagine an RTL designer who is able in minutes to (1) change complex RTL, (2) then update automatically UPF and SDC files and release all changes. This has a great benefit compared to traditional ways of updating manually UPF and SDC databases and different interactions between several teams to get a consistent RTL+UPF+SDC database.
What’s new this year?
Several breakthrough technologies are announced this year. First is around the unified flow as mentioned earlier. We are ready to demonstrate the related value to major semiconductor companies. Also this November at ITC (International Test Conference) in Fort Worth Texas, we will be demonstrating for the first time, a platform which will help exploring at RTL complex DFT architectures to help DFT engineers and DFT architects to decide about how much DFT logic is needed at different levels. The ultimate goal is to fit into an area overhead+test time budget given test coverage criteria. A typical DFT architecture includes test compression, memory BIST, etc.
How will chip companies benefit from Defacto STAR design solution?
Defacto tools are Tcl based and easily customizable to help and interoperate with existing DFT flows. Defacto doesn’t compete with existing DFT offers. Defacto augment existing DFT flows.
What are your major challenges?Is to demonstrate the benefits of this RTL DFT solution on complex chips on real projects, maybe the most important challenge is to convince users to start as early as possible to explore complex RTL design configurations. In other words, changing mindset is one of the challenges we face daily!
Which markets do you feel offer the most and best opportunities for STAR over the next few years and why? Is there a killer app somewhere in these markets?
Several, especially emerging markets. For example, the automotive market is now highly demanding of reliable, secure and testable chips: a higher test coverage where chips are tested when applications are running. This mean DFT requirements are higher. It is one of the reasons why to start building and configuring DFT architectures as soon as possible.
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