Webinar: Understanding Clock Gating Metrics for SpyGlass Power

Webinar: Understanding Clock Gating Metrics for SpyGlass Power
by Bernard Murphy on 09-07-2017 at 4:00 pm

Clock gating is one of the simplest ways to reduce dynamic power in a design. By turning off the clock on a register which is busy doing nothing useful you can eliminate pointless switching power in that register and also in much or all of the following fanout cone of combinational logic. In this way, judicious gating can extend battery… Read More


CEO Interview: Chouki Aktouf of Defacto Technologies

CEO Interview: Chouki Aktouf of Defacto Technologies
by Daniel Nenni on 11-14-2016 at 7:00 am

Image RemovedAs a 30+ year semiconductor veteran I can tell you with 100% certainty that start-ups are the lifeblood of EDA. The mantra is “Innovate or Die!” and that is exactly what Defacto is doing. After more than 10 years of innovating in Design for Test at RTL, Defacto is now offering a complete EDA solution based… Read More