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November 14, 2016

CEO Interview: Chouki Aktouf of Defacto Technologies

CEO Interview: Chouki Aktouf of Defacto Technologies
by Daniel Nenni on 11-14-2016 at 7:00 am
Categories: Defacto Technologies, EDA

Image RemovedAs a 30+ year semiconductor veteran I can tell you with 100% certainty that start-ups are the lifeblood of EDA. The mantra is “Innovate or Die!” and that is exactly what Defacto is doing. After more than 10 years of innovating in Design for Test at RTL, Defacto is now offering a complete EDA solution based… Read More

October 18, 2016

Achieving Lower Power through RTL Design Restructuring (webinar)

Achieving Lower Power through RTL Design Restructuring (webinar)
by Daniel Payne on 10-18-2016 at 4:00 pm
Categories: Defacto Technologies, EDA, Events

From a consumer viewpoint I want the longest battery life from my electronic devices: iPad tablet, Galaxy Note 4 smart phone, Garmin Edge 820 bike computer, and Amazon Kindle book reader. In September I blogged about RTL Design Restructuring and how it could help achieve lower power, and this month I’m looking forward to … Read More

April 19, 2016

A Versatile Design Platform with Multi-Language APIs

A Versatile Design Platform with Multi-Language APIs
by Pawan Fangaria on 04-19-2016 at 7:00 am
Categories: Defacto Technologies, EDA

In one of my whitepapers “SoCs in New Context – Look beyond PPA”, I had mentioned about several considerations which have become very important in addition to power, performance, and area (PPA) of an SoC. This whitepaper was also posted in parts as blogs on Semiwiki (links are mentioned below). Two important… Read More

March 4, 2016

A Brief History of Defacto Technologies

A Brief History of Defacto Technologies
by Pawan Fangaria on 03-04-2016 at 7:00 am
Categories: Defacto Technologies, EDA

In early 2000s, semiconductor design at RTL level was gaining momentum. The idea was to process more design steps such as insertion of test and other design structures upfront at the RTL level. The design optimization and verification were to be done at the RTL level to reduce long iterations through gate level design because changes… Read More

February 24, 2013

At DVCon: Pre-Simulation Verification for RTL Sign-Off includes Automating Power Optimization and DFT

At DVCon: Pre-Simulation Verification for RTL Sign-Off includes Automating Power Optimization and DFT
by Graham Bell on 02-24-2013 at 8:10 pm
Categories: EDA

By now, you will have seen several postings about all the different activities that are going on at Design and Verification Conference being held Feb. 25-28 at its usual location – the DoubleTree Hotel in San Jose, CA. Besides organizing an experts panel “Where Does Design End and Verification Begin?“, Real… Read More

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Response to IP’s Growing Impact On Yield And Reliability
"Excellent article, even for the outsider like me, Thanks."

— Arthur Hanson on October 15, 2019
Acceleration in a Heterogenous Compute Environment
"Interesting note. Thanks for the reference"

— Bernard Murphy on October 14, 2019
Acceleration in a Heterogenous Compute Environment
"Been there... Inmos in the UK tackled the parallel computing problem with CSP back in the 1980s.…"

— simguru on October 14, 2019
Crashing the Mars Rovers!!! Actel and Aerospace Corp
"Hi mike. Glad to hear you saw it that way!!"

— John East on October 12, 2019
Crashing the Mars Rovers!!! Actel and Aerospace Corp
"I recall bragging regularly when I was there to various audiences that Actel devices were on board every lander that…"

— Mike Brogley on October 11, 2019
5G Deployments – The Analysis Requirements are Ginormous
"Some cities are still in the stone age and will take years to just get up to current standards.…"

— Arthur Hanson on October 10, 2019
Acceleration in a Heterogenous Compute Environment
"Very interesting blog. It makes a lot of sense to split up tasks to the most efficient hardware using…"

— Arthur Hanson on October 10, 2019
A Review of TSMC’s OIP Ecosystem
"Is it intentional to show "N10 Full-Coloring Custom Design Flow" slide in Fig 5 ? :)"

— hsienhsinlee on October 9, 2019
A Future Vision for 3D Heterogeneous Packaging
"I guess InFO would reduce latency between chiplets. That would be very useful for AMD's new server CPUs. High latency…"

— lefty on October 9, 2019
A Future Vision for 3D Heterogeneous Packaging
"Yes I do believe TSMC is racing ahead, a generation or two for sure. The entire ecosystem is collaborating with…"

— Daniel Nenni on October 8, 2019

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Concerned about IP security threats for your SoCs? Achronix: Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior Thermal-induced Reliability Challenges and Solutions for Advanced IC Design REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation REPLAY: Avoiding CDM (Charged Device Model) ESD Failures REPLAY: eFPGA – "What a great idea! But I have no idea how I’d use it!" REPLAY: Ensuring System-level Security Through Hardware/Software Security Verification REPLAY: Fabless: The Transformation of the Semiconductor Industry REPLAY: The Brave New World of Customized Memory REPLAY: Embedded FPGA: The Fabric for Optimized Machine Learning REPLAY: VLSI Design Methodology Development REPLAY: Lightspeed Data Sync - Design Workspace Problems Solved! REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats? REPLAY: How ASIC/SoC Prototyping Solutions Can Help You! REPLAY: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso® REPLAY: Taiwan ESD Workshop Recording REPLAY: Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction REPLAY: Text: A Year of Breakfast Bytes by Paul McLellan (Free PDF Version) REPLAY: Finding Your Way Through Verification [filter] => 1 [visual] => 1 [rw_opt] => Array ( [widget_select] => 1 [others_front_page] => 1 [category_96] => 1 [category_6435] => 1 [category_95] => 1 [category_157] => 1 [category_50] => 1 [category_13] => 1 [category_90] => 1 [category_89] => 1 [category_3611] => 1 [category_178] => 1 [category_14418] => 1 [category_51] => 1 [category_97] => 1 [cpt_page] => 1 [others_blog_page] => 1 [category_44] => 1 [category_5] => 1 [category_32] => 1 [category_22] => 1 ) [display_widget_mobile] => 1 )

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Tag: defacto

CEO Interview: Chouki Aktouf of Defacto Technologies

Achieving Lower Power through RTL Design Restructuring (webinar)

A Versatile Design Platform with Multi-Language APIs

A Brief History of Defacto Technologies

At DVCon: Pre-Simulation Verification for RTL Sign-Off includes Automating Power Optimization and DFT

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Semi Industry Creates Ultimate Weapon, Now Ultimate Responsibility

WEBINAR: A Year of Breakfast Bytes by Paul McLellan (Free PDF Version of his book)

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TSMC’s Leading-Edge Fab Investments Set Stage for Sale Surge in 2H19

Platforms, Leverage, Compounding, AI/ML, TSM/Success

VLSI Design Methodology Development Webinar Replay and Follow up Q&A!

TSMC Files Complaints Against GlobalFoundries in U.S., Germany and Singapore for Infringement of 25 Patents!

Deal flow: Device and ioT startups?

Recent Article Comments

Response to IP’s Growing Impact On Yield And Reliability

Acceleration in a Heterogenous Compute Environment

Acceleration in a Heterogenous Compute Environment

Crashing the Mars Rovers!!! Actel and Aerospace Corp

Crashing the Mars Rovers!!! Actel and Aerospace Corp

5G Deployments – The Analysis Requirements are Ginormous

Acceleration in a Heterogenous Compute Environment

A Review of TSMC’s OIP Ecosystem

A Future Vision for 3D Heterogeneous Packaging

A Future Vision for 3D Heterogeneous Packaging