Defacto at the 2025 Design Automation Conference #62DAC

Defacto at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-12-2025 at 8:00 am

62nd DAC SemiWiki

Defacto has been a leading provider of SoC integration tools for large-scale designs for years. Most major semiconductor companies already use their solutions, and several customers will be presenting how they leverage the Defacto solution (SoC Compiler) at the upcoming DAC conference.

This year, Defacto is announcing a major… Read More


SoC Front-end Build and Assembly

SoC Front-end Build and Assembly
by Daniel Payne on 06-09-2025 at 10:00 am

SoC Compiler flow min

Modern SoCs can be complex with hundreds to thousands of IP blocks, so there’s an increasing need to have a front-end build and assembly methodology in place, eliminating manual steps and error-prone approaches. I’ve been writing about an EDA company that focuses on this area for design automation, Defacto Technologies, and … Read More


2025 Outlook with Dr. Chouki Aktouf of Defacto

2025 Outlook with Dr. Chouki Aktouf of Defacto
by Daniel Nenni on 01-21-2025 at 6:00 am

Picture Chouki

Chouki Aktouf is Founder & CEO of Defacto Technologies and Co-Founder of Innova Advanced Technologies.  Prior to founding Defacto in 2003, Dr. Aktouf was an associate professor of Computer Science at the University of Grenoble – France and leader of a dependability research group. He holds a PhD in Electric Engineering from… Read More


2025 Outlook with Dr. Chouki Aktouf of Innova

2025 Outlook with Dr. Chouki Aktouf of Innova
by Daniel Nenni on 01-14-2025 at 10:00 am

Picture Chouki

Chouki Aktouf is Founder & CEO of Defacto Technologies and Co-Founder of Innova Advanced Technologies.  Prior to founding Defacto in 2003, Dr. Aktouf was an associate professor of Computer Science at the University of Grenoble – France and leader of a dependability research group. He holds a PhD in Electric Engineering from… Read More


Build a 100% Python-based Design environment for Large SoC Designs

Build a 100% Python-based Design environment for Large SoC Designs
by Daniel Nenni on 11-11-2024 at 10:00 am

Integrated Python based design environment

In the fast-evolving world of semiconductor design, chip designers are constantly on the lookout for EDA tools that can enhance their productivity, streamline workflows, and push the boundaries of innovation. Although Tcl is currently the most widely used language, it seems to be reaching its limits in the face of the growing… Read More


A Joint Solution Toward SoC Design “Exploration and Integration” released by Defacto #61DAC

A Joint Solution Toward SoC Design “Exploration and Integration” released by Defacto #61DAC
by Daniel Nenni on 07-23-2024 at 6:00 am

flow ip explorer soc compiler (1)

When I was at DAC last month, I had the chance to talk with Chouki Aktouf and Bastien Gratréaux from Defacto and they told me about a new innovative solution to generate Arm-based System-on-Chips. I heard that this solution has now been released.

Defacto and Arm developed a joint SoC design flow to help Arm users cover all needed automation—from… Read More


Innova at the 2024 Design Automation Conference

Innova at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 12:00 pm

DAC 2024 Banner

Design projects are becoming more and more complex. The success of a design project is tightly linked to the best preparation. Having an accurate and precise prediction of either project design resources or design parameters, with a plan to react in an appropriate way is crucial and cost saving.

A typical example is the availability… Read More


Defacto at the 2024 Design Automation Conference

Defacto at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 10:00 am

DAC 2024 Banner

Defacto continues to confirm its SoC Compiler as becoming the “de facto” SoC integration solution for large SoC designs. This year they are coming to DAC to share customer success stories of building the largest SoCs in the market from specification to RTL + collaterals such as UPF by including thousands of IP cores! All done within… Read More


WEBINAR: Joint Pre synthesis RTL & Power Intent Assembly flow for Large System on Chips and Subsystems

WEBINAR: Joint Pre synthesis RTL & Power Intent Assembly flow for Large System on Chips and Subsystems
by Daniel Nenni on 12-11-2023 at 10:00 am

Blog UPF Picture1

Nowadays, low power design requirements are key for large SoCs (system on chips) for different applications: AI, Mobile, HPC, etc. Power intent management early in the design flow is becoming crucial to help facing PPA (Power Performance Area) design challenges.

WEBINAR REGISTRATION

With the increasing complexity of such … Read More


WEBINAR: What Makes SoC Compiler The Shortest Path from SoC Design Specification to Logic Synthesis?

WEBINAR: What Makes SoC Compiler The Shortest Path from SoC Design Specification to Logic Synthesis?
by Daniel Nenni on 05-24-2021 at 6:00 am

SoC compiler puzzle

Defacto SoC Compiler whose 9.0 release was announced recently automates the SoC design creation from the first project specifications. It covers register handling, IP and connectivity insertion at RTL, UPF and SDC file generation right to logic synthesis. As part of the generation process of RTL and design collaterals, basic… Read More