Mentor Graphics will be all over DVCon next week (February 25-28) at the DoubleTree hotel in San Jose.
In addition to attending all the panels, tutorials, posters, and the keynote, you can visit Mentor in booth 901 on the exhibit floor.
Here’s the lineup of Mentor-related events:
Monday, February 25
9:00 AM Tutorial 2 – “Increasing Productivity with SystemC in Complex System Design and Verification,” with Mentor’s John McDonald and Shabtay Matalon.
1:30 PM Tutorial 3 – “Low Power Design, Verification, and Implementation with IEEE 1801™ UPF™,” organized by Mentor’s, Erich Marschner, who is also a presenter.
Tuesday, February 26
9:00 AMSession 1 – Deployment of UCIS.
[*=1]“UCIS Applications: In 3 – Formal and Semi-formal Techniques,” presented by Mentor technologist Ahmed Yehia.
[*=1]“Using Formal Verification to Exhaustively Verify SoC Assemblies,” by Mentor application engineer Mark Handover, and Kenny Ranerup of ST-Erisson.
10:30 AMPoster session
[*=1]“Seven Separate Sequence Styles Speed Stimulus Scenarios”
[*=1]“Using Formal Techniques to Verify SoC Reset Schemes” (with MediaTek co-authors)
[*=1]“Unifying Hardware Assisted Verification and Validation using UVM and Emulation”
[*=1]“Register Verification: Do We Have Reliable Specification?”
[*=1]“Traffic Profiling and Performance Instrumentation for On-Chip Interconnects” (with ARM co-author)
[*=1]“Boosting Simulation Performance of UVM Registers in High Performance Systems”
[*=1]“The Need for Speed: Understanding Design Factors That Make Multi-Core Parallel Simulations Efficient”
[*=1]“Monitors, Monitors Everywhere – Who is Monitoring the Monitors? SystemVerilog UVM Monitors and Scoreboards”
11:30 AM Lunch! Sponsored by Mentor Graphics.
[INDENT=2]For the lunch-time show, Harry Foster of Mentor will present highlights from the recent Wilson Research Group Functional Verification study that identifies the latest verification trends, challenges, and solutions.
1:00 PM Sessions 4, 5, and 6
[*=1]“Using UVM – The Condensed Guide for Designers, Debuggers, Test-Writers, and Other Skeptics,” by Gordon Allan.
[*=1]“Boost Verification Results by Bridging the Hardware/Software Testbench Gap,” by Matthew Balance.
[*=1]“Weathering the Verification Storm: Methodology Enhancements used on a Next Generation Weather Satellite C&DH Program,” by Michael Horn, with Lockheed Martin co-authors.
[*=1]“Sequence, Sequence on the Wall – Who’s the Fairest of Them All? Using SystemVerilog UVM Sequences for Fun and Profit,” by Rich Edelman and Raghu Ardeishar.
3:30 PM Keynote address by Wally Rhines, Chairman and CEO of Mentor Graphics.
Wednesday, February 27
8:30 AMPanel – Where Does Design End and Verification Begin?
Mentor’s Harry Foster is a panelist.
10:30 AMSession 7
“Transaction-Level Friending: An Open-Source, Standards-Based Library for Connecting TLM Models in SystemC and SystemVerilog,” by Adam Erickson.
1:30 AM Session 10, 11, and 12
[*=1]“Guaranteed Vertical Reuse – C Execution in a UVM Environment,” by Alain Gonier of Mentor, with Rachida El-Idrissi of ST-Ericsson.
[*=1]“One Compile to Rule Them All: An Elegant Solution for OVM/UVM Testbench Topologies,” by Steve Chappell.
[*=1]“Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI,” by Dave Rich.
3:30 PM Panel — “Industry Leaders Panel: The Road to 1M Design Starts,” Serge Leef, VP of New Ventures at Mentor Graphics is a panelist.
Thursday, February 28
8:30 AMTutorial 6 – “We’ve Got You Covered: Practical Advice for Achieving Coverage Closure,” organized by Mentor’s Rebecca Granquist. Technologist Tom Fitzpatrick and Questa Product marketing manager Mark Olen are both panelists.
Don’t forget to Register for DVCon, and visit Mentor in booth 901 on the exhibit floor.Share this post via:
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