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Osmosis: OneSpin Meeting on Solutions, Innovation, & Strategy
Presented by OneSpin: A Siemens Business
Osmosis is the name for all users’ group events for customers and partners of OneSpin: A Siemens Business, provider of electronic design automation (EDA) tools for integrated circuit (IC) integrity verification.
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Unreachability (UNR) analysis, finding and definitively proving that certain states in a design cannot possibly be covered in testing, should be a wildly popular component in all verification plans. When the coverage needle stubbornly refuses to move, where should you focus testing creativity while avoiding provably untestable… Read More
The Synopsys VC Formal group have a real talent for finding industry speakers to talk on illuminating outside-the-box-topics in formal verification. Not too long ago I covered an Intel talk of this kind. A recent webinar highlighted use of formal methods used together with a cool technique I have covered elsewhere called Quick… Read More
ABSTRACT:
Formal verification constructs a mathematical proof to verify a design-under-test (DUT) against a requirement. The requirement itself can be expressed in multiple ways. Traditionally, formal methods have required PhDs in Mathematics and CS.
However, modern-day deployment of formal methods can be done with ease… Read More
This event is in-person only — there is no support for remote participation.
Join us to learn new technologies and techniques you can adopt today to increase your verification productivity and get a sneak preview of our roadmap.
Conference program
Start |
Topic |
8:30 |
Check-in and breakfast |
9:30 |
Welcome and overview |
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Synopsys has posted on the SolvNet site a fascinating talk given by Dr. Theo Drane of Intel Graphics. The topic is datapath equivalency checking. Might sound like just another Synopsys VC Formal DPV endorsement but you should watch it anyway. This is a mind-expanding discussion on the uses of and considerations in formal which … Read More
Formal methods for digital verification have advanced enormously over the last couple of decades, mostly in support of verification in control and data transport logic. The popular view had been that datapath logic was not amenable to such techniques. Control/transport proofs depend on property verification; if a proof is … Read More
Summary
For over a decade, CPU and GPU design companies have been using Synopsys VC Formal Datapath Validation (DPV) app with its HECTOR™ technology to verify their data processing elements because traditional verification methods cannot exhaustively verify the correctness of mathematical computations in these designs.
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Synopsys Webinar: Wednesday, November 30, 2022 | 10:00 – 11:00 a.m. Pacific
Finite Impulse Response (FIR) filters are widely used in communication, consumer electronics, and many other digital signal process (DSP) applications. A FIR filter includes a complex pipelined datapath based on arithmetic functions such
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Club Formal Europe 2022by Admin on 10-19-2022 at 2:43 pm