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Bringing Formal Verification into Mainstream

Bringing Formal Verification into Mainstream
by Pawan Fangaria on 04-28-2016 at 7:00 am

Formal verification can provide a large productivity gain in discovering, analyzing, and debugging complex problems buried deep in a design, which may be suspected but not clearly visible or identifiable by other verification methods. However, use of formal verification methods hasn’t been common due to its perceived complexity… Read More


SpyGlass DFT ADV accelerates test closure – Xilinx and Synopsys webinar

SpyGlass DFT ADV accelerates test closure – Xilinx and Synopsys webinar
by Bernard Murphy on 04-26-2016 at 12:00 pm

Fed up with ECOing your way out of test problems? You might want to register for this webinar.When you’re building monster SoC FPGAs, you have all the same problems you have with any other SoC. That includes getting to very high test coverage as quickly as you can with a design targeted to the most advanced processes. We’re not just … Read More


Static Timing Analysis Keeps Pace with FinFET

Static Timing Analysis Keeps Pace with FinFET
by Daniel Payne on 04-22-2016 at 12:00 pm

At SemiWiki we’ve been blogging for several years now on the semiconductor design challenges of FinFET technology and how it requires new software approaches to help chip designers answer fundamental questions about timing, power, area and design closure. When you mention the phrase Static Timing Analysis (STA) probably… Read More


Debugging is the whole point of prototyping

Debugging is the whole point of prototyping
by Don Dingee on 04-15-2016 at 4:00 pm

The prototype is obviously the end goal of FPGA-based prototyping, however success of the journey relies on how quickly defects can be found and rectified. Winning in the debug phase involves a combination of methodology, capability, and planning. Synopsys recently aired a webinar on their HAPS environment and its debug ecosystem.… Read More


Custom Layout Productivity Gets a Boost

Custom Layout Productivity Gets a Boost
by Tom Dillinger on 04-11-2016 at 7:00 am

In the 1970’s, when Moore’s Law was still in its infancy, Bill Lattin from Intel published a landmark paper [1]. In it he identified the need for new design tools and methods to improve layout productivity, which he defined as the drawn and verified number of transistors per day per layout designer. He said existing … Read More


IoT or Smart Everything?

IoT or Smart Everything?
by Daniel Payne on 03-31-2016 at 12:00 pm

I just attended a keynote presentation at SNUG from Aart de Geus, CEO of Synopsys. This event is well attended with some 2,500 people that are learning from the 96 presentations on all things Synopsys, semiconductor. IP, and foundry trends. There are big name sponsors like: GLOBALFOUNDRIES, Samsung, socioeconomic, TSMC, Fujitsu,… Read More


Analog Mixed-Signal Layout in a FinFET World

Analog Mixed-Signal Layout in a FinFET World
by Tom Dillinger on 03-20-2016 at 12:00 pm

The intricacies of analog IP circuit design have always required special consideration during physical layout. The need for optimum device and/or cell matching on critical circuit topologies necessitates unique layout styles. The complex lithographic design rules of current FinFET process nodes impose additional restrictions… Read More


VC Apps Tutorial at DVCon 2016

VC Apps Tutorial at DVCon 2016
by Bernard Murphy on 03-17-2016 at 7:00 am

We might wish that all our design automation needs could be handled by pre-packaged vendor tool features available at the push of a button, but that never was and never will be the case. In the language of crass commercialism, there may be no broad market for those features, even though you consider that analysis absolutely essential.… Read More


Is Smart Bluetooth de facto standard for IoT Wearable, Beacons, Fitness and Health ?

Is Smart Bluetooth de facto standard for IoT Wearable, Beacons, Fitness and Health ?
by Eric Esteve on 03-13-2016 at 7:00 am

Synopsys launch BTLE PHY IP, qualified by the Bluetooth Special Interest Group (SIG) and meeting compliance with the Bluetooth® Smart v4.2 specification. The company has built a partnership with Mindtree to provide a complete solution, integrating Synopsys’ Bluetooth Smart PHY IP and Mindtree’s production-proven BlueLitE… Read More


Verdi Update and NVIDIA on Verification Compiler

Verdi Update and NVIDIA on Verification Compiler
by Bernard Murphy on 03-11-2016 at 12:00 pm

Synopsys hosted a lunch session on Thursday of DVCon. Michael Sanie of Synopsys opened the session, with a look back at the last DVCon where he had talked about Verification Compiler (VC) and extending the platform to Verification Continuum, which adds emulation and FPGA-based prototyping (HAPS – there was a very cool HAPS demo… Read More