Silos to Systems Webinar Banner Ad 800x100 (1)
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4342
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4342
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)
EDA

Electronic Design Automation

Posted on

Apache Power Artist Capabilities II

Apache Power Artist Capabilities II
by Paul McLellan on 12-09-2012 at 4:00 pm
Categories: Ansys, Inc., EDA

This is the second part of my discussion with Paul Traynar, Apache’s PowerArtist guru. The first part discussed sequential reduction capabilities. Part I was here.

There are two big challenges with doing power analysis at the RTL level. Firstly, how do you get an accurate enough model of what the design will dissipate given… Read More

Posted on

Subsystem IP, myth or reality?

Subsystem IP, myth or reality?
by Eric Esteve on 12-07-2012 at 5:00 am
Categories: Cadence, IP

I have participated to a panel during IP-SoC, I must say that “Subsystem IP, myth or Reality” was a great moment. The panel was a mix of mid-size IP vendor (CAST, Sonics), one large EDA (Martin Lund from Cadence), Semiwiki blogger and one large IDM (Peter Hirt from STM) who has very well represented the customer side. And, to make the… Read More

Posted on

Yield Analysis and Diagnosis Webinar

Yield Analysis and Diagnosis Webinar
by Beth Martin on 12-06-2012 at 10:02 pm
Categories: EDA, Siemens EDA

Sign up for a free webinar on December 11 on Accelerating Yield and Failure Analysis with Diagnosis.

The one hour presentation will be delivered via webcast by Geir Eide, Mentor’s foremost expert in yield learning. He will cover scan diagnosis, a software-based technique, that effectively identifies defects in digital logic… Read More

Posted on

Apache Power Artist Capabilities I

Apache Power Artist Capabilities I
by Paul McLellan on 12-06-2012 at 2:05 pm
Categories: Ansys, Inc., EDA

I sat down last week with Paul Traynar who was over from UK. He is Apache’s PowerArtist guru. The first thing we talked about was PowerArtist’s sequential power reduction capabilities.

Forward propagation of enables means that when a register is clock gated and feeds a downstream register then that register can be… Read More

Posted on

A Brief History of the Fabless Semiconductor Ecosystem

A Brief History of the Fabless Semiconductor Ecosystem
by Daniel Nenni on 12-05-2012 at 7:00 pm
Categories: EDA, Foundries, IP

Clearly the fabless semiconductor ecosystem is driving the semiconductor industry and is responsible for both the majority of the innovation and the sharp decline in consumer electronics costs we have experienced. By definition, a fabless semiconductor company does not have to spend the time and money on manufacturing related… Read More

Posted on

Microprocessor Test and Verification 2012

Microprocessor Test and Verification 2012
by Paul McLellan on 12-05-2012 at 5:43 pm
Categories: EDA

Next week December 10-12th is the Microprocessor Test and Verification (MTV 2012) which is in Austin Texas (as DAC will be next year, of course). After lunch on Monday there is a panel session on the effectiveness of virtual prototyping entitled When simulation suffices, who needs FPGA or emulation? Bill Neifert, the CTO of Carbon… Read More

Posted on

Formal Analysis of Security Data Paths

Formal Analysis of Security Data Paths
by Paul McLellan on 12-05-2012 at 5:07 pm
Categories: EDA

One challenge with security in systems is to ensure that there are not backdoors, either accidentally or maliciously inserted. Intel, ARM and others have various forms of trusted execution technology. Under the hood these are implemented by dividing the design into two parts, normal and secure, and implementing them with physical… Read More

Posted on

Double Patterning Exposed!

Double Patterning Exposed!
by SStalnaker on 12-04-2012 at 7:15 pm
Categories: EDA, Siemens EDA

Wanna become the double patterning guru at your company? David Abercrombie, DFM Program Manager for Calibre, has written a series of articles detailing the multifaceted impacts of double patterning on advanced node design and verification. For designers struggling to understand the complexity and nuances of double patterning,… Read More

Posted on

SystemC vs C++ for High Level Synthesis

SystemC vs C++ for High Level Synthesis
by Paul McLellan on 12-04-2012 at 4:00 pm
Categories: EDA

One of the decisions that needs to be made when using high-level synthesis (HLS) in general and Catapult in particular is what language to use as input. The choice is C++ or SystemC. Of course at some level SystemC is C++ with added libraries and templates, but in fact the semantics of the two languages end up being very different.

The… Read More

Posted on

An FPGA Design Flow with Aldec Tools

An FPGA Design Flow with Aldec Tools
by Daniel Payne on 12-04-2012 at 12:19 pm
Categories: Aldec, EDA, FPGA

I’ve used FPGA vendor-supplied tools from both Xilinxand Lattice Semibefore, so I wanted to see what EDA tools Aldec has to offer for FPGA design. I read the Aldecwhite paper, Corporate Standardization of FPGA Design Flow, and summarize what I found.… Read More