Banner Electrical Verification The invisible bottleneck in IC design updated 1
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4324
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4324
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)
EDA

Electronic Design Automation

Posted on

Tanner EDA Tops 1,200 Active Customers!

Tanner EDA Tops 1,200 Active Customers!
by Daniel Nenni on 11-22-2012 at 8:33 pm
Categories: EDA, Tanner EDA

It is always nice to see when an EDA company grows organically, versus inorganically by acquiring friends and foes. It is also nice to see when an EDA company invests in the fabless semiconductor ecosystem because, as we know, we are all in this together.

Tanner EDA celebrated its 25th anniversary this year by adding 149 new customers… Read More

Posted on

Apache on Signal Integrity

Apache on Signal Integrity
by Paul McLellan on 11-20-2012 at 1:09 pm
Categories: Ansys, Inc., EDA

Matt Elmore has a two-part blog about the growing complexity of signal integrity analysis, both on the chip itself and the increasingly complex analysis required to make sure that signals (and power) get in and out of the chip from the board cleanly, especially to memory, which requires simultaneous analysis of chip-package-system… Read More

Posted on

EDS Fair: Dateline Yohohama

EDS Fair: Dateline Yohohama
by Paul McLellan on 11-20-2012 at 12:22 pm
Categories: EDA

Electronic Design and Solutions Fair (EDSF) was held in Yokohama Japan from Wednesday to Friday last week. It was held at the Pacifico Hotel, somewhere I have stayed several times, not far from the Yokohama branch of Hard Rock Cafe and, what used to be at least, the biggest ferris-wheel in the world.

Atrenta was one of the many companies… Read More

Posted on

How much SRAM proportion could be integrated in SoC at 20 nm and below?

How much SRAM proportion could be integrated in SoC at 20 nm and below?
by Eric Esteve on 11-20-2012 at 4:45 am
Categories: IP, Synopsys

Once upon a time, ASIC designers were integrating memories in their design (using a memory compiler being part of the design tools provided by the ASIC vendor), then they had to make the memory observable, controllable… and start developing the test program for the function, not a very enthusiastic task (“AAAA” and “5555” and other… Read More

Posted on

Mentor and NXP Demonstrate that IJTAG Can Reduce Test Setup Time for Complex SoCs

Mentor and NXP Demonstrate that IJTAG Can Reduce Test Setup Time for Complex SoCs
by glforte on 11-15-2012 at 8:10 pm
Categories: EDA, Siemens EDA

The creation of test patterns for mixed signal IP has been, to a large extent, a manual effort. To improve the process used to test, access, and control embedded IP, a new IEEE P1687 standard is being defined by a broad coalition of IP vendors, IP users, major ATE companies, and all three major EDA vendors. This new standard, also called… Read More

Posted on

What I Learned About FPGA-based Prototyping

What I Learned About FPGA-based Prototyping
by Daniel Payne on 11-15-2012 at 8:10 pm
Categories: Aldec, EDA, FPGA

Today I attended an Aldec webinar about ASIC and SoC prototyping using the new HES-7 Board. This prototyping board is based on the latest Virtex-7 FPGA chips from Xilinx.

You can view the recorded webinar here, which takes about 30 minutes (should be available in a few days). I first blogged about the HES-7 two months ago, ASIC Prototyping… Read More

Posted on

Test and Diagnosis at ISTFA

Test and Diagnosis at ISTFA
by Beth Martin on 11-15-2012 at 7:10 pm
Categories: EDA, Siemens EDA

Finding and debugging failures on integrated circuits has become increasingly difficult. Two sessions at ISTFA (International Symposium for Testing and Failure Analysis) on Thursday address the current best practices and research directions of diagnosis.

The first was a tutorial this morning by Mentor Graphics luminary… Read More

Posted on

Creating Plug-and-Play IP Networks in Large SoCs with IEEE P1687 (IJTAG)

Creating Plug-and-Play IP Networks in Large SoCs with IEEE P1687 (IJTAG)
by glforte on 11-14-2012 at 2:15 pm
Categories: EDA, Siemens EDA

Until now, the integration and testing of IP blocks used in large SOCs has been a manual, time consuming design effort. A new standard called IEEE P1687 (or “IJTAG”) for IP plug-and-play integration is emerging to simplify these tasks. EDA tools are also emerging to support the new standard. Last week mentor announcedTessent IJTAG,… Read More

Posted on

The logic of trusting FPGAs through DO-254

The logic of trusting FPGAs through DO-254
by Don Dingee on 11-13-2012 at 8:15 pm
Categories: Aldec, EDA, FPGA

Any doubters of the importance of FPGA technology to the defense/aerospace industry should consider this: each Airbus A380 has over 1000 Microsemi FPGAs on board. That is a staggering figure, especially considering the FAA doesn’t trust FPGAs, or the code that goes into them.… Read More

Posted on

Jasper User Group Keynotes

Jasper User Group Keynotes
by Paul McLellan on 11-13-2012 at 1:31 pm
Categories: EDA

I attended the Jasper User Group this week, at least the keynotes, the first by Kathryn Kranen the CEO of Jasper and the second by Bob Bentley of Intel.

Kathryn went over some history, going back to when the company was started (under the name Tempus Fugit) back in August 2002 with a single product for protocol verification. Now, since… Read More