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WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4172
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4172
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)
EDA

Electronic Design Automation

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Getting the Most Out of the ARM CoreLink™ NIC-400

Getting the Most Out of the ARM CoreLink™ NIC-400
by Daniel Payne on 10-28-2013 at 12:27 pm
Categories: EDA

SoC designers are attracted to ARM as an IP provider because of their popular offerings and growing ecosystem of EDA partners like Carbon Design Systems. At the upcoming ARM Techcon on October 31 this week in Santa Clara you’ll have an opportunity to hear a joint presentation from ARM and Carbon Design Systems on: Getting … Read More

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Cadence’s Mixed-Signal Technology Summit

Cadence’s Mixed-Signal Technology Summit
by Randy Smith on 10-28-2013 at 1:45 am
Categories: Cadence, EDA

On October 10, I attended another Cadence Summit, this one titled the Cadence Mixed-Signal Technology Summit. Recently, I had written about the Cadence Silicon Verification Summit. The verification event was the first of its kind, and I thought it had terrific content. Being more of a digital guy myself, I was unaware that Cadence… Read More

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An easier way to deal with design rule waivers (video)

An easier way to deal with design rule waivers (video)
by Beth Martin on 10-26-2013 at 11:00 am
Categories: EDA, Siemens EDA

At advanced nodes, design rules are necessarily more complex and restrictive. Although most of the time you can find a way to live with them, sometimes it’s necessary to seek a waiver from the foundry for a particular design feature. This involves documenting the feature, the design rules in question and the conditions under which… Read More

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An Affair to Remember: EDA’s 50th Anniversary

An Affair to Remember: EDA’s 50th Anniversary
by Daniel Nenni on 10-26-2013 at 11:00 am
Categories: EDA, Events

What an amazing night! I celebrated the 50[SUP]th[/SUP] anniversary of the industry I grew up in! With my beautiful wife at my side and a table full of friends we all went down memory lane, ate, drank, and then enjoyed the auction.

The tour of the new computer museum was amazing. I was learning so much up until the 1970’s, then … Read More

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TSMC ♥ Synopsys (HSPICE)

TSMC ♥ Synopsys (HSPICE)
by Daniel Nenni on 10-24-2013 at 5:05 am
Categories: EDA, Synopsys

In case you haven’t noticed, Synopsys has been in the press lately talking about their relationship with TSMC. Since I’m an internationally recognized industry expert they gave me a call for a briefing and I was happy to do it. Staying connected with the #1 EDA company is important and fun since I get to ask questions that most people… Read More

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Webinar on IP Lifecycle Management

Webinar on IP Lifecycle Management
by Daniel Payne on 10-23-2013 at 5:44 pm
Categories: EDA, Perforce

EDA and Semiconductor companies are offering new webinars almost every week of the year, so there’s always something worth learning about that only takes an hour of time. On November 5th there’s an interesting webinar planned on the topic of IP Lifecycle Management, hosted by Methodics. I blogged two weeks ago about,… Read More

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Kathryn: "Formal Will Dominate Verification"

Kathryn: "Formal Will Dominate Verification"
by Paul McLellan on 10-23-2013 at 4:16 pm
Categories: EDA

At the Jasper Users’ Group meeting, Kathryn presented the state of Jasper. The numbers are impressive. The company has grown at a CAGR of over 35% since 2007, which is 6 times faster than EDA as a whole. They have been profitable at 15-20% EBITDA for 14 consecutive quarters.

Jasper is focused on engaging deeply with a small number… Read More

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Hierarchical Clock Domain Crossing

Hierarchical Clock Domain Crossing
by Paul McLellan on 10-23-2013 at 1:31 pm
Categories: EDA

One of the first blogs I wrote on SemiWiki was on clock domain crossing (CDC). I thought it was rather a specialized subject, a sort of minority interest. It turned out to be one of the most-read blogs I’ve written. Modern SoCs have lots of unrelated clocks, maybe hundreds, and so ensuring that signals going from one clock domain… Read More

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EM Solver and Visualization Essential for Device Design

EM Solver and Visualization Essential for Device Design
by Daniel Nenni on 10-22-2013 at 5:00 pm
Categories: EDA

In many designs, an on chip inductor is created as though it were simply a device with an L and a Q value. Of course this view would seem to make life simpler for designers and the tools they use. But in reality even a simple inductor is really a complex compound structure with many electromagnetic elements interacting in complex ways.… Read More

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The Biggest Private EDA Company

The Biggest Private EDA Company
by admin on 10-21-2013 at 5:02 pm
Categories: EDA

I talked this morning with fellow Brit David Halliday. More importantly, he is CEO of Silvaco, which he thinks must be the biggest private EDA company in the world. He didn’t reveal their revenue numbers but they have around 250-300 people and are profitable so you can make your own estimate.

David became CEO when Ivan Pesic,… Read More