hip webinar automating integration workflow 800x100 (1)
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EDA

Electronic Design Automation

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Improving Design Practices for an Image Sensor IDM

Improving Design Practices for an Image Sensor IDM
by klujan on 05-07-2013 at 8:30 pm
Categories: EDA, Tanner EDA

With nearly twenty five years in business, Tanner EDA Application Engineers have seen a wide range of support requests. One consistent topic area is around design data management and design reuse. In one recent instance, our customer, an IDM who produces imaging sensors for infrared vision systems, called on Tanners AE team for… Read More

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How To Design a TSMC 20nm Chip with Cadence Tools

How To Design a TSMC 20nm Chip with Cadence Tools
by Paul McLellan on 05-07-2013 at 8:10 pm
Categories: Cadence, EDA, Foundries, TSMC

Every process node these days has a new “gotcha” that designers need to be aware of. In some ways this has always been the case but the changes used to be gradual. But now each process node has something discontinuously different. At 20nm the big change is double patterning. At 14/16nm it is FinFET.

Rahul Deokar and John… Read More

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Bangers: the Best Beer Bar in Austin; Live Oak Brewing, the Best Beer in Austin

Bangers: the Best Beer Bar in Austin; Live Oak Brewing, the Best Beer in Austin
by Paul McLellan on 05-07-2013 at 8:10 pm
Categories: EDA, Events

OK, enough with all this semiconductor geeky stuff. The important thing about DAC is…where to go to eat to avoid standard issue convention center chicken Caesar salad.

And a 7 minute walk from the convention center is Bangers Sausage House and Beer Gardenwhere you can have the $8 “executive” lunch consisting… Read More

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Wireless Algorithm Validation from System to RTL to Test

Wireless Algorithm Validation from System to RTL to Test
by Daniel Nenni on 05-07-2013 at 8:05 pm
Categories: Aldec, EDA

LSK 1123

This year’s #50DAC will be chock-full of technical content because that is what attracts the masses of semiconductor professionals, like moths to a flame, or like me to a Fry’s Electronics store. Interesting note, I went to high school with Randy Fry. His Dad started the Fry’s supermarket chain which he sold… Read More

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Cell-Aware Test Seminar

Cell-Aware Test Seminar
by Beth Martin on 05-07-2013 at 8:05 pm
Categories: EDA, Siemens EDA

You may have heard about cell-aware testing. It’s a transistor-level test (ATPG) methodology that is quickly becoming a hot topic. If you are involved in DFT and are looking for better quality and reliability, you should definitely know about cell-aware testing.


And lucky you, on May 16, 2013, you can attend a free seminar on cell-aware… Read More

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Global Foundries Does DAC

Global Foundries Does DAC
by Paul McLellan on 05-07-2013 at 8:05 pm
Categories: EDA, Foundries, GlobalFoundries

Global Foundries will be at DAC in booth 1314. There will be 6 pods there demonstrating:

  • Advanced Technology: 28nm ready and ramping, and next is 20LPM and 14XM.
  • PDKs: For 28nm, 20nm and 14nm. 14nm handles FinFET enablement complexity. Robust, easy to use and high quality, supports pretty much the full range of EDA tools.
  • Design
… Read More
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A Brief History of Dassault Systèmes

A Brief History of Dassault Systèmes
by Paul McLellan on 05-07-2013 at 8:05 pm
Categories: Dassault Systemes, EDA

Dassault Systèmes (DS) was created in 1981 when a small team of engineers were spun out of Dassault Aviation. They were developing software to design wind-tunnel models and so reduce the cycle time for wind-tunnel testing, using surface modeling in 3D instead. The company entered into a distribution agreement with IBM that same… Read More

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Sage Design Automation iDRM Launch

Sage Design Automation iDRM Launch
by Daniel Nenni on 05-07-2013 at 7:00 pm
Categories: EDA, Sage DA

This is an example of what I do during the day. I work with emerging companies on disruptive technologies and help launch them into the fabless semiconductor ecosystem. This product, iDRM, is the result of three years of joint development work amongst three semiconductor foundries and some of their top customers:… Read More

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Sandisk and NetworkComputer

Sandisk and NetworkComputer
by Paul McLellan on 05-07-2013 at 12:33 pm
Categories: EDA

Robert Veltman and Vikash Tyagi of SanDisk Corporation presented at SNUG a few weeks ago on their selection and use of RTDA’s NetworkComputer to manage their workflows.

Like everyone else, SanDisk has a high-performance computing farm (and like everyone else they are coy about how big it is) and lots of licenses for EDA tools,… Read More

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Training Day at DAC

Training Day at DAC
by Paul McLellan on 05-07-2013 at 12:15 pm
Categories: EDA, Events

This year for the first time the Thursday of DAC is tranining day. So that would be June 6th in Austin, of course. There are four tracks of training focused on SystemC, ARM Cortex and two on SystemVerilog, all areas of increasing use in SoC design, especially in mobile.

Each track of training is divided into two parts, one held from 9am… Read More