I am a believer of continuous improvement in anything we do; it’s pleasant to see rapid innovation in technology these days, especially in semiconductor space – technology, design, tools, methodologies… Imagine a 100K gates up to 1M gates design running at a few hundred MHz frequency and at technology node in the range of .18 to .35 microns in late 1990s and early 2000 when designers were struggling to optimize PPA and shorten design cycle time. Synopsys pioneered RTL to gate level synthesis which proved to be very successful. Today, with a billion gates SoC, operating at GHz frequencies, fabricated at cutting edge technology nodes, it is imperative one has to optimize PPA at system level. True, FinFET technology at 14nm provides excellent PPA, but that has huge cost and dynamic power implications. SoC verification cost has gone up tremendously. It’s time; we look at ways to optimize power and other critical success criteria at system level (not necessarily for FinFET nodes) and also reduce burgeoning design and verification cost including that of running huge regressions through large server farms.
I admire, people did have foresight on High Level Synthesis (HLS) in the form of behavioral compiler in 1990s. Then in 2004, Mentorunveiled Catapult which synthesized pipelined, multi-block subsystems from C/C++. During the same period, Forteintroduced Cynthesizer which synthesized hardware from SystemC. Continuous refinements went down the line to address design issues such as control logic improvements, power optimization, levels of timing abstractions (TLM standard came up) and so on. Other HLS tools such as CadenceC-to-Silicon also came up. These tools actually demonstrated the value of high level synthesis in terms of top-down design methodology from system level that optimized design architecture and cut down design time significantly. However, wider adoption of the HLS tools in design community was distant because they catered to specific type of hardware designs that exhibited mostly one-way data movement. The other reason was lame economic and business push to adopt HLS amid several issues to be resolved there.
Calyptowhich was excelling in SLEC (Sequential Logic Equivalence Check) and PowerPro (Power optimization tool at RTL) found complementary value in Catapult and acquired it from Mentorin 2011 to provide a comprehensive HLS solution. Since then Catapult is proving well in providing value for differentiated IP in video processing, image processing and advanced communication area. Recently by using Catapult Googlewas able to reduce the design time by half for their VP9 video decoder design and further they collaborated with VeriSiliconwhere it was very easy to share C code between them.. Now there is critical mass of designers seeing value in HLS that can optimize design architecture for best PPA at system level, reduce design time by large extent, accelerate verification and debugging at C/SystemC level, and facilitate collaboration and reuse through sharing of technology and architecture neutral designs. By using Catapult, customers have seen significant saving in area (up to 18%) and time (up to 16x) at best QoR of their designs.
However, HLS is still not a mainstreamdesign methodology, why? Recent surveyconducted by Calypto shows that designers need more control for design closure and seamless flow with their RTL verification, choice of C++ or SystemC and also learning through use of HLS. What’s Calypto doing to address these issues now?
The first of its kind in the 3[SUP]rd[/SUP] generation of HLS, Calypto announced Catapult 8 Platform that has unmatched capabilities to make designers more productive through HLS. In my brief telephonic call with Sanjiv Kaul, CEO at Calypto, Mark Milligan, VP of Marketing and Bryan Bowyer, Catapult 8 Product Engineering, I learnt that this newly architected product is a result of multi-year investment in Catapult since 2011. Interestingly, before this full production release, Calypto migrated its major partner customers to Catapult 8 through limited access release in 2014. Naturally, the active key designers’ input has been taken to architect this platform! What’s new?
Unlike older generation of HLS where any incremental change in C++/SystemC could lead to a very different RTL, now with configurable hierarchical design architecture of Catapult 8, designers will have full control over design hierarchy where they can assemble the design in top-down or bottom-up fashion, synthesize and verify individual blocks at a time while keeping rest of the design locked and import Verilog or VHDL IP as needed. This methodology provides automatic as well as designer controlled synthesis that provides 10x capacity improvement in design assembly and synthesis.
Catapult 8 moves the verification up and addresses designers’ major concern about C and RTL mismatches by synthesizing assertions and cover points, identifying and guaranteeing key equivalent points, providing cross-probing between RTL and C++/SystemC and using integrated formal tools to identify unreachable states. With Catapult 8, designers are able to obtain full RTL verification coverage, that has been a requirement for wide spread adoption of HLS. The methodology provides full functional coverage at much reduced (100x to 1000x) server need and smaller code to debug. Also it provides integration with verification flows based on industry standard methodologies such as UVM.
The platform is flexible to accept C++ or SystemC; designers may use both on different projects. Catapult LP, available on Catapult 8 platform provides power optimized RTL which uses Calypto’s patented deep sequential analysis technology and also enables designers to try different microarchitectures to explore low power.
What’s more? Catapult 8 includes a brand new Catapult Catware library of pre-built, synthesizable components that can be used for faster deployment and adoption of HLS. Expect widespread adoption of HLS with this new innovative platform! Stay tuned to hear more details on the specific state-of-the-art capabilities in Catapult 8.Share this post via: