#57DAC – Panel Discussion of High Level Synthesis

#57DAC – Panel Discussion of High Level Synthesis
by Daniel Payne on 07-28-2020 at 10:00 am

sean dart, Cadence

Presenters took a trip down memory lane at DAC this year by having a panel discussion on HLS (High Level Synthesis) spanning from 1974 to 2020, and that time period aligns with when I first graduated from the University of Minnesota in 1978, starting chip design at Intel, then later transitioning into EDA companies by 1986. MarilynRead More


Leveraging HLS/HLV Flow for ASIC Design Productivity

Leveraging HLS/HLV Flow for ASIC Design Productivity
by Pawan Fangaria on 12-23-2015 at 12:00 pm

Imagine how semiconductor design sizes leapt higher with automation in digital design, which started from standard hardware languages like Verilog and VHDL; analog design automation is still catching up. However, it was not without a significant effort put in moving designers from entering schematics to writing RTL, which… Read More


HLS – Major Improvement through Generations

HLS – Major Improvement through Generations
by Pawan Fangaria on 12-02-2014 at 6:30 pm

I am a believer of continuous improvement in anything we do; it’s pleasant to see rapid innovation in technology these days, especially in semiconductor space – technology, design, tools, methodologies… Imagine a 100K gates up to 1M gates design running at a few hundred MHz frequency and at technology node in the range of .18 to … Read More


Calypto AMD Renesas and #50DAC

Calypto AMD Renesas and #50DAC
by Daniel Nenni on 05-28-2013 at 10:00 am

This year for DAC, Calypto has assembled an impressive lineup of customer presentation, suite sessions and Designer Tracks. To start with customer presentation, Steve Kommrusch, Fellow Design Engineer from AMD will be giving a talk in the Calypto Suite on AMD’s methodology for low power and will show how AMD was able to get further… Read More