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WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4174
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4174
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)

Capturing Analog Design Intent with Verification

Capturing Analog Design Intent with Verification
by Daniel Payne on 12-08-2013 at 10:05 am

Analog IC designers are gradually adopting what digital IC designers have been doing for years, metric driven verification. When you talk with analog designers about their methodology and approach, you hear terms like artisan being used which implies mostly a manually-oriented methodology. Thanks to automation from EDA companies,… Read More


Virtual Prototypes Made Easier for SoC Design

Virtual Prototypes Made Easier for SoC Design
by Daniel Payne on 12-06-2013 at 6:24 pm

Using a virtual prototype for your SoC design is accepted, conventional wisdom today because it can save development time by eliminating design iterations and avoid costly bugs that will cause an expensive product recall. In order to simulate your virtual prototype you need models, so a major question has always been, “Where… Read More


Physically Aware Synthesis

Physically Aware Synthesis
by Paul McLellan on 12-06-2013 at 2:47 pm

Yesterday Cadence had their annual front-end summit, the theme of which was physically aware design. I was especially interested in the first couple of presentations about physically aware synthesis. I joined Cadence in 1999 when they acquired Ambit Design Systems. One of the products that we had in development was called PKS… Read More


What Makes A Designer’s Day? A Bottleneck Solved!

What Makes A Designer’s Day? A Bottleneck Solved!
by Pawan Fangaria on 12-04-2013 at 3:00 pm

In an environment of SoCs with tough targets of multiple functionalities, smallest size, lowest power and fastest performance to achieve within a limited design cycle window in order to meet the rigid time-to-market requirements, any day spent without success becomes very frustrating for a designer. Especially during tape-out… Read More


SPICE Development Roadmap 2013!

SPICE Development Roadmap 2013!
by Daniel Nenni on 12-04-2013 at 11:00 am


The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, delivered its annual autumn compact modeling workshop on Sept. 20, 2013 as an integral part of the ESSDERC/ESSCIRC Conference in Bucharest (RO). The event received full sponsorship from leading industrial partners including Agilent… Read More


Cadence & ARM Optimize Complex SoC Performance

Cadence & ARM Optimize Complex SoC Performance
by Pawan Fangaria on 12-03-2013 at 3:00 pm

Now a day, a SoC can be highly complex, having 100s of IPs performing various functionalities along with multi-core CPUs on it. Managing power, performance and area of the overall semiconductor design in the SoC becomes an extremely challenging task. Even if the IPs and various design blocks are highly optimized within themselves,… Read More


Webinar: Parasitic Debugging made easy!

Webinar: Parasitic Debugging made easy!
by Daniel Nenni on 12-03-2013 at 3:00 pm

We cordially invite you to attend this webinar and learn how to quickly debug post layout designs. Concept Engineering is a privately held company based in Freiburg, Germany. It was, founded in 1990 to develop and market innovative schematic generation and viewing technology for use with logic synthesis, verification, test … Read More


Simplified Assertion Adoption with SystemVerilog 2012

Simplified Assertion Adoption with SystemVerilog 2012
by Daniel Payne on 12-02-2013 at 7:01 pm

SystemVerilog as an assertion language improved and simplified with the 2012 version compared to the 2005 version. I recently viewed a webinar on SystemVerilog 2012 by consultant Srinivasan Venkataramanan, who works at CVC Pvt. Ltd. There’s been a steep learning-curve for assertions in the past, and hopefully you’ll… Read More


Conquering errors in the hierarchy of FPGA IP

Conquering errors in the hierarchy of FPGA IP
by Don Dingee on 12-02-2013 at 10:00 am

FPGA design today involves not only millions of gates on the target device, but thousands of source files with RTL and constraints, often generated by multiple designers or third party IP providers. With modules organized in some logical way describing the design, designers brace themselves for synthesis and a possible avalanche… Read More


Because X doesn’t always mark the exact spot

Because X doesn’t always mark the exact spot
by Don Dingee on 11-30-2013 at 1:00 pm

Digital hardware has a habit of deciding – based on the bias and behavior of transistors – to drive outputs to a 0, or a 1, or if commanded a high-impedance Z state. SystemVerilog recognizes a fourth state: X, the “unknown” state a simulator has trouble inferring.

Simulators have a choice. Under X-optimism, they can convert the unknown… Read More