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Tektronix at #50DAC

Tektronix at #50DAC
by Daniel Nenni on 05-13-2013 at 10:00 am

If we grew up in similar eras you will know Tektronix as a company that manufactures test and measurement devices. Every lab I was in during high school and college had Tek oscilloscopes and logic analyzers. At #50DAC however, attendees that visit Tektronix will experience firsthand RTL simulation-level visibility to multi-FPGA… Read More


Cliosoft CEO on Design Collaboration Challenges!

Cliosoft CEO on Design Collaboration Challenges!
by Daniel Nenni on 05-12-2013 at 8:30 pm

Cliosoft was one of the first SemiWiki subscribers and it is a pleasure to work with them. They have one of the busiest landing pages with more than 30 articles authored by Daniel Payne, Paul McLellan, and myself. Srinath and I have lunch occasionally and exchange ideas, observations, and experiences:

Q: What are the specific designRead More


A Big Boost for Equivalency Checking

A Big Boost for Equivalency Checking
by Daniel Payne on 05-12-2013 at 1:41 pm

Thirty years ago in 1983 Professor Daniel Gajski and Kuhn created the now famous Y-Chart to show the various levels of abstraction in electronic system design:

We can still use this Y-Chart today because it still pertains to how engineers are doing their SoC designs. Along the Behavioral axis there is a need to know that each level… Read More


iDRM Brings Design Rules to Life!

iDRM Brings Design Rules to Life!
by Pawan Fangaria on 05-11-2013 at 8:00 pm

Much awaited, automatic tool for DRM (Design Rule Manual) and DRC (Design Rule Check) deck creation is here now! I am particularly excited to know about this because I had been hearing for its need (in different context) from the designers with whom I was working to improve their design productivity through the use of our EDA tools… Read More


Winning in Monte Carlo: Managing Simulations Under Variability and Reliability

Winning in Monte Carlo: Managing Simulations Under Variability and Reliability
by Daniel Nenni on 05-11-2013 at 7:00 pm

I recently talked to Trent McConaghy about his book on variation-aware design of custom ICs and the #50DAC tutorial we are doing:

Winning in Monte Carlo: Managing Simulations Under Variability and Reliability.

Trent is the Solido Chief Technology Officer, an engaging speaker, one of the brightest minds in EDA, and someone who… Read More


Calypto, in Three Part Harmony

Calypto, in Three Part Harmony
by Paul McLellan on 05-11-2013 at 8:00 am

As Julius Caesar said, “Gallia est omnis divisa in partes tres.” All Gaul is divided into 3 parts. Calypto is similar with three product lines that work together to provide a system level approach to SoC design. Two of those product lines are not unique, in the sense that similar capabilities are available from a handful… Read More


Prototyping Over 100 Million ASIC Gates Capacity

Prototyping Over 100 Million ASIC Gates Capacity
by Daniel Payne on 05-10-2013 at 12:42 pm

Most SoCs today are being prototyped in FPGA hardware before committing to costly IC fabrication. You could just design and build your own FPGA prototyping system, or instead choose something off the shelf and then concentrate on your core competence of SoC design.

Thanks to the FPGA vendors like Xilinx we now have FGPA prototyping… Read More


Is my Library or Semi IP really OK to use?

Is my Library or Semi IP really OK to use?
by Daniel Payne on 05-10-2013 at 11:42 am

The tremendous growth in IC and SoC design complexity has now enabled engineers to place bilions of transistors on a single chip. To make that growth possible design teams resort to using libraries and semi IP provided by other groups in their company, or outside IP vendors. To lower risk, you must know that the IP being used in your… Read More


Forte CEO on Design and Verification Complexity

Forte CEO on Design and Verification Complexity
by Daniel Nenni on 05-10-2013 at 9:00 am

Sean Dart’s first DAC (Las Vegas) was as a customer in 1989. Designs were hitting 15,000 gates back then so he was looking for better schematic editors and simulators for gate level design. Fast forward 25 years and Sean’s customers are doing 15,000,000 gate subsystems and that number is growing steadily every year.… Read More


Modern SoC designs require a placement- and routing-aware ECO solution to close timing

Modern SoC designs require a placement- and routing-aware ECO solution to close timing
by Jamie Chen on 05-09-2013 at 9:30 pm

As an applications engineer for over 15 years supporting physical design tools that enable implementation closure, I have seen the complexity of timing closure grow continuously from one process node to the next. At 28nm, the number of scenarios for timing sign-off has increased to the extent that is way beyond the number that … Read More