Nvidia designs some of the most powerful graphics chips and systems in the world, so I’m always eager to learn more about their IC design methodology. This week I’ve had the chance to talk with Ting Ku, Director of Engineering at Nvidia about his DAC talkin the Apache booth in exactly two weeks from today. Registration… Read More
Electronic Design Automation
The Only DM Platform Integrated with All Major Analog and Custom IC Design Flows
As I have mentioned before, Cliosoft is the biggest little company in EDA with the most talked about products on SemiWiki. At DAC, ClioSoft will introduce integrated SOS design management (DM) solutions providing revision control, design management and multi-site team collaboration for Aglient Technologies’ Advanced Design… Read More
Transistor-Level Update from Cadence at DAC
My 8 years as an IC circuit designer were at the transistor-level, so if that interests you as well then consider what there is to see from Cadence at DAC this year. IC design technology is changing quickly, so keeping up to date is important for your job security and continual education goals.
Here’s what I would recommend attending… Read More
Samsung’s Life of Pi @ Apache @ DAC
Last week I talked to Eileen You of Samsung-SSI to get a preview on what they will be talking about at Apache’s customer theater at DAC. Their presentation is titledThe Life of PI: SoC Power Integrity from Early Estimation to Design Sign-off. The ‘PI’ stands for Power Integrity.
Samsung-SSI’s operations… Read More
Tempus: Cadence Takes On PrimeTime
Today Cadence announced Tempus, their new timing signoff solution. This has been in development for at least a couple of years and has been built from the ground up to be massively parallelized. Not just that different corners can be run in parallel (which is basically straightforward) but that large designs can be partitioned … Read More
Design Data Management – Key Winning Strategy!
In a complex semiconductor market today, characterized by ever increasing design size and complexity, long design cycle, rapid technological advancement, intense competition, pricing pressure, small window of opportunity, development and cross-functional teams spread across the globe and multiple design partners including… Read More
CEO Interview: Jens Andersen of Invarian
Invarian is an interesting EDA company that sees a niche market opening in the physical verification space. There are a number of converging factors driving this opportunity. Electromigration and voltage-drop for full-chip analysis demands SPICE level accuracy with fast runtimes. Invarian solves that problem with macro … Read More
Complete Schedule of Synopsys 2013 DAC Events, Panels & Paper Participation (Free Food!)
Funny story, @ #49DAC I saw Aart with a very relaxed look on his face looking at the exhibit hall and in my mind he was thinking, “Mine, all mine!” But I digress……. Synopsys is the #1 EDA company for a reason and here is the supporting data for that hypothesis:
Synopsys is committed to accelerating Innovation… Read More
BDA Introduces High-Productivity Analog Characterization Environment (ACE)
Last week Berkeley Design Automation introduced a new Analog Characterization Environment (ACE) – a high-productivity system to ensure analog circuits meet all specifications under all expected operational, environmental, and process conditions prior to tapeout.
While standard cell characterization and memory characterization… Read More
Oasys Announces Floorplan Compiler
Today Oasys announced the availability of Floorplan Compiler in the Oasys RealTime suite of physical RTL exploration and synthesis tools. This is actually a repackaging of a capability that has always been in RealTime Designer, and in fact has been an important aspect of how well RealTime Designer has performed in benchmarks … Read More
Real men have fabs!