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Electronic Design Automation
Cadence announced their Q4 and 2014 results yesterday. They are the only one of the big 3 EDA companies whose fiscal year is the calendar year so Synopsys and Mentor will not be joining them in announcing them this week.
I won’t go into the numbers in detail, you can find them all easily enough. But it is a pity that statements like… Read More
In the late 1990s I was the VP Engineering at Ambit Design Systems. We had a synthesis product (called BuildGates, nobody ever forgot the name). Both our own engineers and our customers wanted to be able to take a look at the gate-level netlist that was generated from their RTL. We used a product from a company called Concept Engineering… Read More
The 40[SUP]th[/SUP] SPIE Advanced Lithography conference will be at the San Jose Convention Center 22-26 February. Over the past few years, this conference has grown in scope to include emerging patterning technologies, like directed self-assembly (DSA) and design-process-technology co-optimization.
Underlying all … Read More
With increasing density and functionality of chips at extremely thin silicon and metal layers, temperature has become critical. The temperature situation can become worse with wireless enabled 24/7 power-on devices. In such a scenario, a device must manage its thermal profile dynamically to keep the temperature within tolerable… Read More
I talked to Derek Kimpton of Silvaco today. He turns out to be a fellow Brit. He is presenting a webinar on total dose that is of interest to anyone creating chips that will go into space (primarily satellites), or near space (primarily avionics in planes). Pretty much everyone knows at least the basics of single-event-effects (SEE)… Read More
Advanced skill in auto repair, carpentry, plumbing, and similar trades often correlates to one factor. Knowing what you want to do is one thing – having the proper tool is another, and can make the difference. Many a job has extended from minutes to hours over the lack of the right tool at the right moment. Experienced mechanics and… Read More
When I hear the phrase Static Timing Analysis (STA) the first EDA tool that comes to mind is PrimeTimefrom Synopsys, and this type of tool is essential to reaching timing closure for digital designs by identifying paths that are limiting chip performance. Sunil Walia, PrimeTime ADV marketing lead spoke with me by phone on Thursday… Read More
As of today NVM IP has been mostly used in SoC or IC to support very specific needs like analog trimming and calibration or encryption key integration for Digital Right Management (DRM) purpose. In other words small size (less than 1K-bit) few times programmable (FTP) NVM IP was enough to support these needs, thus most of the NVM IP… Read More
DNA sequencing — which provides vital information on genetics study, forensics, diagnostics and therapies — has been an exclusive territory of high-end research labs with millions of dollars to spend because of the expensive chemical and optical equipment needed for research. That is changing, thanks to complex… Read More
When chip designers moved from a gate-level design methodology to coding with RTL there was a learning curve involved, and the same thing happens when you move from RTL to High Level Synthesis (HLS) using C++ or SystemC coding. One great shortcut to this learning curve is the use of pre-defined library functions. I just heard about… Read More
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