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EDA

Electronic Design Automation

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Dealing with FPGA IP in all its forms

Dealing with FPGA IP in all its forms
by Don Dingee on 02-12-2015 at 10:00 pm
Categories: EDA, FPGA, Synopsys

One of the recurring themes I see here in the pages of SemiWiki and elsewhere is this pitched, bordering on religious battle between Altera and Xilinx. Just because both are FPGA technologies, the tendency is to put them in the same bucket, drawing direct comparisons between them. Some folks say there is no comparison; Xilinx has… Read More

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ADAS Going Mainstream One Chip at a Time

ADAS Going Mainstream One Chip at a Time
by Majeed Ahmad on 02-12-2015 at 1:00 pm
Categories: EDA, IoT, STMicroelectronics

Advanced Driving Assistance Systems (ADAS) are an essential element in the vision of autonomous or semi-autonomous vehicles, and they are becoming available today. The ADAS automotive technology raises driving safety by detecting obstacles around the vehicle such as other vehicles and pedestrians, as well as traffic signs… Read More

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How Well is HSPICE Tracking Current Design Trends?

How Well is HSPICE Tracking Current Design Trends?
by Tom Simon on 02-11-2015 at 10:00 pm
Categories: EDA, Synopsys

For about 5 years now Synopsys has held an HSPICE SIG event in conjunction with DesignCon. It features a small vendor faire with companies that partner with Synopsys on HSPICE flows. They also have a dinner with industry/customer speakers and provide an update on HSPICE development. Lastly there is a Q&A where customers get… Read More

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UVM Debugging Made Easy & Productive in Questa

UVM Debugging Made Easy & Productive in Questa
by Pawan Fangaria on 02-11-2015 at 2:00 pm
Categories: EDA

As design complexity and size is increasing, SoC verification has become one of the most difficult and time consuming tasks in the design closure.UVM (Universal Verification Methodology, an accellera initiative) is one of the best verification methodologies that support common language, coherent strategy, clarity and transparency… Read More

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Chips Are Going 3D, DRC Needs to Go 3D Too

Chips Are Going 3D, DRC Needs to Go 3D Too
by Paul McLellan on 02-10-2015 at 7:00 am
Categories: Coventor, EDA

The last paradigm shift in DRC was around 0.35um when designs got too large to handle as flat data, and hierarchical approaches were required. Back then the design rules themselves were not that complex, the explosion of data volume came from the complexity of the design itself. But each process node added more design rules intricacies… Read More

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Open Forum for Semiconductor Professionals!

Open Forum for Semiconductor Professionals!
by Daniel Nenni on 02-09-2015 at 8:00 pm
Categories: EDA, Foundries, IP, Semiconductor Services

The semiconductor industry has never been more exciting than it is today, at least not in my 30 years of experience. Things are moving faster than ever before making collaboration at all levels a requirement. At SemiWiki we are afforded the privilege of passes to semiconductor conferences around the world. We also have access to… Read More

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Writing the unwritten rules with ALINT-PRO-CDC

Writing the unwritten rules with ALINT-PRO-CDC
by Don Dingee on 02-09-2015 at 11:30 am
Categories: Aldec, EDA

EDA verification tools generally do a great job of analyzing the written rules in digital design. Clock domain crossings (CDCs) are more like those unwritten rules in baseball; whether or not you have a problem remains indefinite until later, when retaliation can come swiftly out of nowhere.

Rarely as overt or dramatic as a bench-clearing… Read More

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A Public Synchronizer

A Public Synchronizer
by Jerry Cox on 02-09-2015 at 7:00 am
Categories: EDA

You might ask yourself “Why would anyone want to have a public synchronizer available to download?” Usually designers just grab a flip-flop from his or her company’s or a standard cell vendor’s library. However, are these handy solutions the best course of action today? Current SoC designs have numerous clock domains providing… Read More

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Integrated Spec Design & Documentation for SoC

Integrated Spec Design & Documentation for SoC
by Daniel Payne on 02-08-2015 at 1:00 pm
Categories: EDA, Magillem

One challenge in SoC projects is maintaining consistency between the specification, design and documentation throughout the product lifecycle. Imagine the chaos if your specification for power is 300 mW, the design is actually 350 mW and the documentation promises 250 mW. Traditionally the design and documentation process… Read More

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Why Would You Leave Yahoo to Go Into EDA?

Why Would You Leave Yahoo to Go Into EDA?
by Paul McLellan on 02-06-2015 at 7:00 am
Categories: EDA, Perforce

I sat down this afternoon with Peter Theunis, the CTO of Methodics. Conveniently their office is about a 15 minute walk from where I live so we could chat face to face.

Peter started programming when he was 8 and his first “product” was a weather system for orchards where sensors in the orchards would send information … Read More