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Electronic Design Automation
Who’s doesn’t like a good webinar? I certainly do as it is one of the most time efficient ways to interact with the fabless semiconductor ecosystem, absolutely. Especially when it addresses two of the top trending topics on SemiWiki and they are ARM and FD-SOI. Here is a quick summary of what you will learn:
GLOBALFOUNDRIES… Read More
I talked with Paul Cunningham (VP front-end digital R&D) at CDNLive recently to get a Cadence perspective on digital design trends. He sees needs from traditional semiconductor companies evolving as usual, with disruption here and there from consolidation. But on the system side there is explosion in demand – for wearables,… Read More
We introduced the philosophy behind the Blue Pearl Software suite of tools for front-end analysis of ASIC & FPGA designs in a recent post. As we said in that discussion, effective automation helps find and remedy issues as each re-synthesis potentially turns up new defects. Why do Blue Pearl users say their tool suite is easier… Read More
In one of my whitepapers “SoCs in New Context – Look beyond PPA”, I had mentioned about several considerations which have become very important in addition to power, performance, and area (PPA) of an SoC. This whitepaper was also posted in parts as blogs on Semiwiki (links are mentioned below). Two important… Read More
The impact of process variation at advanced nodes is increasing — no surprise there. In recent years, the principal design emphasis to better reflect this variation has been the adoption of two new methodologies: (1) advanced on-chip variation (AOCV, as well as POCV/LVF) for digital static timing analysis, and (2) advanced… Read More
Next week is the Mentor U2U Conference in Silicon Valley. By chance I had coffee with one of the U2U keynote speakers while we were waiting for the FD-SOI Symposium to start last week and can tell you this FREE event is one you don’t want to miss:… Read More
The prototype is obviously the end goal of FPGA-based prototyping, however success of the journey relies on how quickly defects can be found and rectified. Winning in the debug phase involves a combination of methodology, capability, and planning. Synopsys recently aired a webinar on their HAPS environment and its debug ecosystem.… Read More
Following Moore’s Law down to 10 or even 7 nm labeled feature size demands US $ hundreds of millions of up-front investment, a very large design team and two or more years of development time. These parameters suggest that it only makes sense for very high volume applications to continue on the shrink path to increase SoCs’ functionalities.… Read More
The EDA Consortium (EDAC) has changed name for Electronic Systems Design Alliance (ESD Alliance). That’s a good reminder that IC are developed (thanks to Design Automation) to be integrated into a System. A wide design ecosystem support system development, including embedded software, design intellectual property (IP), … Read More
While pushing Moore’s Law’s boundaries in the world of 2D packaging, companies are starting to explore nontraditional approaches towards designing integrated circuit chips. 2D packaging is currently the most used method in designing chips in the industry, and while it leads in efficiency of power and performance, it lacks … Read More
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Five Billion Pulses Later: What DUV Optics Testing Reveals About Semiconductor Tool Uptime