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Webinar: How to Implement an ARM Cortex-A17 Processor in 22FDX 22nm FD-SOI Technology

Webinar: How to Implement an ARM Cortex-A17 Processor in 22FDX 22nm FD-SOI Technology
by Daniel Nenni on 04-22-2016 at 7:00 am

 Who’s doesn’t like a good webinar? I certainly do as it is one of the most time efficient ways to interact with the fabless semiconductor ecosystem, absolutely. Especially when it addresses two of the top trending topics on SemiWiki and they are ARM and FD-SOI. Here is a quick summary of what you will learn:

GLOBALFOUNDRIES
Technical Webinar Series:

How to Implement an ARM Cortex-A17 Processor in 22FDX 22nm FD-SOI Technology

Moore’s Law has progressed unabated for decades, pushing the laws of physics and helping to power unprecedented innovation throughout the world. Soon science fiction will become reality, as the fastest, most computationally powerful devices will have transistors consisting only of a molecule and a few atoms. However, the best solution isn’t always the biggest chip with the smallest, fastest transistors. For the mobile, pervasive and intelligent computing space, other factors such as ultra-low-power consumption and RF integration have equal or higher priority. For these applications, GLOBALFOUNDRIES 22FDX platform with 22nm fully depleted silicon-on-insulator (FD-SOI) technology offers optimized, differentiated solutions, with an optimal combination of performance, low power and cost.

One of the essential building blocks of these apps is a high-performance, low-power processor. This webinar outlines the physical architecture considerations and physical design steps of implementing an ARM Cortex-A17 quad-core processor in 22FDX FD-SOI technology, including:

  • Digital implementation flow with industry-standard EDA tools
  • Application of body-bias for specific design intents and scenarios
  • Initial PPA results of an ARM Cortex sub-module
  • Analysis of details and results, including comparison to a 28nm implementation

Adopting a technology platform usually includes a new design flow. Not in this case, since the 22FDX digital design flow is similar to the bulk flow with support from all of the major EDA vendors. The flows use EDA techniques (implant-aware, source/drain-aware, double patterning, UPF support) which have been deployed on earlier nodes. This case uses the Cadence tool suite from initial design creation to signoff.

GLOBALFOUNDRIES design IP for the ARM Cortex-A17 processor includes standard cell base cells, power management cells, and cache memory instances, each with support for body-biasing. Strategic use of software-controlled, dynamic body-biasing enables specific application scenarios and optimization criteria to be applied on a block-by-block basis, resulting in optimized tradeoffs of performance and power. Sample scripts show how this is done.

The concept of an optimizable technology platform is great, but PPA results are what really counts. The performance and power consumption of 22FDX 22nm FD-SOI with body-bias compared to 28nm bulk technologies? This implementation shows ~30% higher frequency at the same power. Optimized for power reduction, there is ~45% power reduction at the same frequency. Both optimizations have ~45% area reduction. The implementation of an ARM Cortex-A9 sub-module based on an initial release of the Invecas 8-track continuous RX standard cell library shows significant boost in frequency and power efficiency compared to 28SLP.

The 22FDX platform is ready to adopt for new designs, with the starter kit of 22FDX digital design flow available now. More information including webinars and white papers are available at GLOBALFOUNDRIES.com/22fdx.

Also Read: ARM and FD-SOI are like Peanut Butter and Jelly!

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