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“Thinking Outside the Chip”

“Thinking Outside the Chip”
by Students@olemiss.edu on 04-13-2016 at 7:00 am

 While pushing Moore’s Law’s boundaries in the world of 2D packaging, companies are starting to explore nontraditional approaches towards designing integrated circuit chips. 2D packaging is currently the most used method in designing chips in the industry, and while it leads in efficiency of power and performance, it lacks in the utilization of space which is always a concern in the chip industry. 2.5D and 3D packaging capitalizes on the use of space, which increases the capacity of chips to hold more transistors per unit area without an increase in the cross-area of the chip. With this advantage, 2.5D and 3D packaging have the potential to jump 2D packaging in the future.

Traditional 2D packaging predominantly refers to System-on-Chip (SoC) and System-in-Packages(SiP). SoC is a device that contains a package that holds one die that contains multiple functions. Due to having only one die, SoC demand low power to be used and has fast circuit operation; however, it is viewed that it is very difficult to design and alter. The whole SoC has to be replaced to add a function for the SoC to perform and a complete replacement is needed if a function does not work correctly. SiP contains one wafer that is connected to multiple individual dice by flip-chip bumps which are essentially solder bumps. The multiple individual dice are on the same wafer. Unlike SoC, SiP are flexible to be altered since they contain individual dice for different functions. The speed of SiP is slower than SoC due to more connections from the individual dice, which increases the chances for failing.

2.5D packaging is very similar to 2D packaging, except that 2.5D packaging uses a silicon interposer to connect the dice to the wafer. Silicon interposer contains a substrate that has metallic components on the sides. It uses through-silicon vias(TSVs) as tunnels to connect metallic sides of the silicon interposer. The dice are connected to the interposer with micro-bumps instead of the larger flip-chip bumps, and the silicon interposer is connected to the substrate with flip-chip bumps. Since TSVs use direct connections, 2.5D use less power to communicate with different components. The silicon interposer also limits the space needed for the use of rails. Adding the silicon interposer introduces additional cost and difficulty to designing and testing.

3D packaging involves the use of multiple dice stacked on top of each other using TSVs to connect the individual dice and the wafer. By using TSVs, the dice are able to interact with each other and the wafer. Due to the thin nature of the TSVs used, 3D packaging utilizes efficient use of space that is used to increase the capacity of the chip for containing more transistors per unit area compared to 2D packaging. The use of TSVs also leads to efficient communications between the die and better performance in terms of power since less power is needed for transmitting signals. Due to dice being stacked upon each other, heat dissipation is one of the major issues with 3D packaging. When the dice are stacked, high temperatures can cause the dice to melt. Additional problems involve the cost of testing since all current chip testing mechanisms are for 2D. The additional costs involved will lead to an increase in the price of the chips which will be divergence from the long trend of cost reduction in the chip industry.

Even though the 2D packaging is the main design being used in manufacturing, the 2.5D and 3D will eventually pass 2D packaging. The boundaries of Moore’s Law dealing with 2D packaging will soon be reached; therefore, 2.5D and 3D will be the future to increasing the amount of transistors per area. Since 3D packaging incorporates more dice per cross-area than 2D packaging, 3D will be the main leader for designs in the future. Despite the performance enhancements that these new packaging approaches bring, there are economic, and technical challenges that need to be navigated through before wide scale implementation in the market.

The economic challenges come from the added costs involved in making these new designs. The new designs involve die integration which costs more. The current existing testing structures are not suitable for the new designs. Although 2.5D design can use most of the existing 2D testing structures, 3D will require a complete overhaul which will be an added cost to the chip industry. The additional production cost will translate into higher prices for chips which is against the tradition of producing cheaper chips in the chip industry.[4] Since the dies are stacked upon each other, heat dissipation, which will causes the dices to melt, is a main issue. Until companies develop a new design that deals with the heat and the rising production costs involved, 3D packaging will continue to lag behind 2D and 2.5D packaging.

By Demba Komma and James Grantham

Article in question for reference:
[1]Sperling, Ed. “Thinking Outside The Chip.” Semiconductor Engineering. N.p., 14 Jan. 2016. Web. 23 Feb. 2016. .

[2]Santarini, Mike. “2.5D ICs Are More than a Stepping Stone to 3D ICs | EE Times.” EETimes. N.p., 27 Mar. 2012. Web. 19 Feb. 2016. <http://www.eetimes.com/document.asp?doc_id=1279514>.
[3] Maxfield, Clive. “2D vs. 2.5D vs. 3D ICs 101 | EE Times.” EETimes. N.p., 8 Apr. 2012. Web. 19 Feb. 2016. .
[4]Bailey, Brian. “When Will 2.5D Cut Costs?” Semiconductor Engineering. N.p., 7 Aug. 2014. Web. 19 Feb. 2016. <http://semiengineering.com/will-2-5d-reduce-costs/>.

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