I have written multiple articles about this year’s SPIE Advanced Lithography Conference describing all of the progress EUV has made in the last year. Source power is improving, photoresists are getting faster, prototype pellicles are in testing, multiple sites around the world are exposing wafers by the thousands and more. The current thinking is that EUV will be ready for production around 2018. All of this is very promising but while we have been waiting for EUV the industry has been moving on and a possible scenario is emerging where by the time EUV is available it won’t be very useful. In the balance of this article I will lay out a possible scenario where changes in device structures and fabrication processes could make EUV largely unnecessary.
My Advanced Lithography Articles summarizing the recent progress of EUV are available here:
- TSMC and Intel on the Long Road to EUV
- ASML and IMEC EUV Process
- Intel EUV Photoresist Progress and ASML High NA EUV
There are three major product categories that drive capital equipment purchases in the semiconductor industry today, NAND Flash, DRAM and Logic.
For many years NAND Flash drove the requirement for the latest lithography tools. 2D NAND Flash devices went through lithography shrinks yearly eventually reaching 16nm devices manufactured in high volume with Self Aligned Quadruple Patterning (SAQP), but difficulties with 2D NAND device scaling and the cost of the complex patterning schemes required have brought 2D NAND scaling to an end. Specifically, adjacent cell interference, control to floating gate coupling and the shrinking number of electrons in a cell are just some of the device related issues. The solution to this issue for NAND has been the move to 3D. 3D NAND creates strings of NAND cells vertically with the cells created by alternating layers of material deposited using CVD techniques. The lithography requirements for 3D NAND are relaxed, for example Samsung’s 32-layer part has only one double patterned layer. Scaling is accomplished by adding layers, not by shrinking the photolithography defined dimensions. It is expected that scaling to >100 layers will yield devices with over 1Tb of capacity. 3D NAND has therefore made EUV unnecessary for NAND.
DRAM has followed a path similar to 2D NAND with yearly shrinks and the use of complex multi-patterning schemes. Recently DRAM scaling has slowed due to device scaling issues. DRAM stores values as a charge or absence of charge on a capacitor fabricated in series with an access transistor that controls the capacitor. Access transistors need a relatively long channel length to minimize leakage. This has led to a variety of access transistor structures such as RCAT, SRCAT and Saddle fin. The next step in access transistor scaling is expected to be VCAT but to-date fabrication of the vertical VCAT has been difficult to achieve. In parallel to this the DRAM capacitors need to scale down in horizontal area while maintaining a minimum acceptable capacitance value. Capacitor scaling to-date has involved vertical structures, rough surfaces and high-k dielectrics. Further vertical scaling has been limited by mechanical issues. and there is also a fundamental trade-off between the dielectric constant (k) of a material and band gap. As k increases the band gap decreases leading to leakage problems. Achieving acceptable leakage through the capacitor constrains the materials that can be used. There are some options still available, for example bit line optimization may allow smaller capacitance values to be used and there are rumors of a new film. At present the device scaling issues have moved DRAM away from being a leading candidate for EUV usage. DRAM also appears to be a leading area of Directed Self Assembly (DSA) research.
Longer term a DRAM alternative is needed. Conventional wisdom is that STT MRAM will eventually replace DRAM. To-date MRAM density and therefore cost is not competitive with DRAM (and there are other developmental issues). MRAM cells are fabricated in the metal layers over logic devices opening up the possibility to move to some kind of 3D Structure, possibly similar to the recently disclosed 3D XPoint memory (more on that later).
In the logic space the leading companies, Intel, TSMC, Samsung and Global Foundries are all in production of 16nm/14nm FinFETs. 10nm is expected to start to enter use in late 2016 at the foundries and in late 2017 at Intel. TSMC is currently forecasting that 7nm will be available in late 2017. TSMC is guiding that they will “exercise” EUV at 10nm for 5nm use. Intel is leaving the door open on EUV use at 7nm and assuming they don’t produce 7nm until 2019 or later that would make sense. Global Foundries has said they are developing 7nm based on what they can reasonably do without EUV and EUV would be a possible second generation 7nm cost reduction. All of this lines EUV up for a projected late 7nm node or 5nm node insertion.
Against this backdrop it is interesting to look at the evolution of logic devices. Intel introduced FinFETs at 22nm, shrunk them for their second generation at 14nm and they are guiding that at 10nm the third generation FinFETs will not have new materials. 16nm/14nm at the foundries was the first generation FinFET for all of them, 10nm will be the second generation and 7nm the third generation FinFETs for them (we should note here that from a pitch perspective the foundries 7nm “node” is similar to Intel’s 10nm node). At one time I thought we might start to see FinFETs with high mobility channels by 7nm or possibly even 10nm but due to a variety of challenges achieving high performance with high mobility channels in actual devices and the challenge of changing an existing structure to a new material I am now thinking FinFETs will likely stay with silicon channels until they are replaced by a new device. This leads to the question of when we might see a new devices and what it might look like.
IMEC is one of, if not the leading semiconductor technology research institution in the world. IMEC appears to be settling in on stacked horizontal nanowires as the successor to FinFETs. The devices experts I talk to are also optimistic on this approach. Horizontal nanowires are fabricated by depositing a stack of alternating materials using CVD techniques and then pattering them. This technique can create a stack of multiple nanowires. One really intriguing possibility is for example to create a 4 nanowire stack where 2 wires are NMOS and 2 are PMOS. This would yield a stacked CMOS devices and be equivalent to a node or more of scaling without shrinking the lithographic dimensions. If you take this idea a step further to 8 stacked wires you could have a stack of two CMOS pairs. You could also look at stacking layers while relaxing the horizontal width to scale the device density while taking the pressure off of lithography to provide shrinks. This would be analogous to what has been done with 3D NAND.
Of course we also need to look at when this might happen. My best guess is around 5nm at least for the foundries. With the foundries lining up to not use EUV at 7nm or only late in 7nm, if a 5nm solution emerges that doesn’t need EUV how much of a EUV investment are they likely to make. For Intel I am thinking horizontal nanowires might be a 7nm solution but with Intel now on a 3-year node cadence that would put Intel’s 7nm node at around 2020 likely around when the foundries would be introducing their 5nm nodes.
The picture all this paints is that NAND no longer drives the need for EUV by going to a 3D structure and logic also has the potential to move to a 3D structure with relaxed requirements. DRAM scaling has slowed due to device scaling issues and is a leading DSA candidate, so what will drive the need for EUV?
Intel and Micron recently introduced their 3D XPoint memory architecture. Faster and with better endurance than NAND and cheaper than DRAM, 3D XPoint is positioned to be used as Storage Class Memory – a kind of buffer between DRAM main memory and non-volatile storage such as NAND and hard disc drives. The first 3D XPoint memory has 2 memory layers fabricated in the interconnect stack over a logic circuit that controls the memory. We estimate the memory layers take 2 mask layers each and are a 25nm technology requiring multipattering for each layer. 3D XPoint scaling offers the ability to scale by adding layers and also by shrinking the memory layer pitch. If 3D XPoint is scaled simply by adding memory layers EUV might not be interesting. If 3D XPoint were to begin scaling pitch, EUV would become attractive. With 3D XPoint not expected to be in production until 2017 and then needing to become established in the market it is hard to envision 3D XPoint successfully driving EUV adoption.
This is of course just one possible scenario for the direction of semiconductor technology but clearly while we have been waiting for EUV the industry has been moving forward on other fronts. Multipattering also continues to get better and cheaper. By 2018 when EUV is currently projected to be ready for production it is possible the evolution of semiconductor devices may make it unnecessary.