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EDA

Electronic Design Automation

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3D TCAD Simulation for Power Devices

3D TCAD Simulation for Power Devices
by Daniel Payne on 08-30-2019 at 10:00 am
Categories: EDA

Silvaco: Split Gate, Figure 1

My first IC design back in 1978 was a DRAM and it ran on 12V, 5V and -5V, but then my second DRAM was using only a 5V supply. Today we see SOCs running under a 1V supply voltage, but there is a totally different market for power devices that are at the other end of the voltage spectrum and they handle switching ranges from 12V – 250V. … Read More

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Lint for Implementation

Lint for Implementation
by Bernard Murphy on 08-29-2019 at 6:00 am
Categories: Cadence, EDA

Conformal Litmus

When I was at Atrenta, we took advantage of opportunities to expand our static tool (aka linting) first to clock domain crossing (CDC) analysis and DFT compatibility and later to static analysis of timing constraints, all of which have importance in implementation. CDC is commonly thought of as an RTL-centric analysis, however,… Read More

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Tensilica DNA 100 Brings the AI Inference Solution for Level 2 ADAS ECUs and Level 4 Autonomous Driving

Tensilica DNA 100 Brings the AI Inference Solution for Level 2 ADAS ECUs and Level 4 Autonomous Driving
by Randy Smith on 08-27-2019 at 10:00 am
Categories: Cadence, Events, IP

I recently wrote about Tensilica’s HiFi DSPs which played a significant role at Cadence’s Automotive Design Summit which was held on the Cadence San Jose campus at the end of July. That article focused on infotainment while briefly touching on Advanced Driver-Assistance Systems (ADAS). ADAS is NOT synonymous with autopilot.… Read More

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Build More and Better Tests Faster

Build More and Better Tests Faster
by Bernard Murphy on 08-27-2019 at 5:00 am
Categories: Breker Verification Systems, EDA, Security
3 Comments

Breker has been in the system test synthesis game for 12 years, starting long before there was a PSS standard. Which means they probably have this figured out better than most, quite simply because they’ve seen it all and done it all. Breker is heavily involved in and aligned with the standard of course but it shouldn’t be surprising… Read More

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Achieving Functional Safety through a Certified Flow

Achieving Functional Safety through a Certified Flow
by Daniel Payne on 08-26-2019 at 10:00 am
Categories: EDA, Perforce

Methodics: Tool and process certification

Functional safety (FuSa) is a big deal, especially when driving a car. My beloved 1998 Acura RL recently exhibited a strange behavior at 239K miles, after making a turn the steering wheel would stay tilted in the direction of the last turn instead of straightening out. The auto mechanic pinpointed the failure to the ball joints, … Read More

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Speeding up Circuit Simulation using a GPU Approach

Speeding up Circuit Simulation using a GPU Approach
by Daniel Payne on 08-22-2019 at 10:00 am
Categories: EDA, Empyrean, Events

ALPS-GT

The old adage that “Time is Money” certainly rings true in the semiconductor world where IC designers are being challenged with getting their new designs to market quickly, and correctly in the first spin of silicon. Circuit designers work at the transistor-level, and circuit simulation is one of the most time-consuming… Read More

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Making pre-Silicon Verification Plausible for Autonomous Vehicles

Making pre-Silicon Verification Plausible for Autonomous Vehicles
by Daniel Payne on 08-20-2019 at 10:00 am
Categories: Automotive, EDA, Siemens EDA

AV diagram

I love reading about the amazing progress of autonomous vehicles, like when Audi and their A8 model sedan was the first to reach Level 3 autonomy, closely followed by Tesla at Level 2, although Tesla gets way more media attention here in the US. A friend of mine bought his wife a car that offers adaptive cruise control with auto-braking,… Read More

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Xilinx on ANSYS Elastic Compute for Timing and EM/IR

Xilinx on ANSYS Elastic Compute for Timing and EM/IR
by Bernard Murphy on 08-20-2019 at 5:00 am
Categories: Ansys, Inc., EDA, FPGA, Xilinx

RedHawk-SC

I’m a fan of getting customer reality checks on advanced design technologies. This is not so much because vendors put the best possible spin on their product capabilities; of course they do (within reason), as does every other company aiming to stay in business. But application by customers on real designs often shows lower performance,… Read More

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Tensilica HiFi DSPs for What I Want to Hear, and What I Don’t Want to Hear

Tensilica HiFi DSPs for What I Want to Hear, and What I Don’t Want to Hear
by Randy Smith on 08-16-2019 at 10:00 am
Categories: Cadence, IP

It seems every day we see a new article (or ten) on autonomous driving. It is an especially hot topic, and it will happen someday. For now, we can dream about it, and many people are working on it. But for the present, the technology in a car that commands my attention is audio. I’ve been a musician since 4th grade. I still perform occasionally… Read More

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Can a hierarchical Test flow be used on a flat design?

Can a hierarchical Test flow be used on a flat design?
by Tom Simon on 08-15-2019 at 10:00 am
Categories: EDA, Siemens EDA

It is pretty common for physical layout to work from a flattened hierarchy for blocks or even full chips, even though the front-end design starts with a hierarchical representation. This was not always the case. Way back when, the physical layout matched the logical hierarchy during the design process. Of course, this led to all… Read More