WP_Term Object
(
    [term_id] => 45
    [name] => Aldec
    [slug] => aldec
    [term_group] => 0
    [term_taxonomy_id] => 45
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 102
    [filter] => raw
    [cat_ID] => 45
    [category_count] => 102
    [category_description] => 
    [cat_name] => Aldec
    [category_nicename] => aldec
    [category_parent] => 157
    [is_post] => 
)
WIKI Multi FPGA Design Partitioning 800x100 
WP_Term Object
(
    [term_id] => 45
    [name] => Aldec
    [slug] => aldec
    [term_group] => 0
    [term_taxonomy_id] => 45
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 102
    [filter] => raw
    [cat_ID] => 45
    [category_count] => 102
    [category_description] => 
    [cat_name] => Aldec
    [category_nicename] => aldec
    [category_parent] => 157
    [is_post] => 
)
Aldec
Posted on

Aldec extends FPGA and ASIC flows at DAC

Aldec extends FPGA and ASIC flows at DAC
by Don Dingee on 05-20-2016 at 4:00 pm
Categories: Aldec, EDA

Aldec tools and services have long been associated with FPGA designs. As FPGAs have evolved toward more RTL-based designs, the similarities between a modern FPGA verification flow and an ASIC verification flow often leave them looking virtually the same. … Read More

Posted on

Webinar alert – VHDL guru says its time to move up

Webinar alert – VHDL guru says its time to move up
by Don Dingee on 04-28-2016 at 4:00 pm
Categories: Aldec, EDA

Many years ago when I worked for Ed Staiano at Motorola, I learned never to use the word “comfortable” in a career context. I’m comfortable being with family and friends. This new high-back chair I sit in at my new faux-cocobolo desk (slightly distressed chalk-painted wood and industrial piping, awesome) is comfortable,… Read More

Posted on

Webinar alert – Taking UVM to the FPGA bank

Webinar alert – Taking UVM to the FPGA bank
by Don Dingee on 04-08-2016 at 4:00 pm
Categories: Aldec, EDA

UVM has become a preferred environment for functional verification. Fundamentally, it is a host based software simulation. Is there a way to capture the benefits of UVM with hardware acceleration on an FPGA-based prototyping system? In an upcoming webinar, Doulos CTO John Aynsley answers this with a resounding yes.… Read More

Posted on

Design units come to faster Riviera-PRO release

Design units come to faster Riviera-PRO release
by Don Dingee on 03-11-2016 at 4:00 pm
Categories: Aldec, EDA

For the latest incremental improvements to its Riviera-PRO functional verification platform, Aldec has turned to streamlining random constraint performance. The new Riviera-PRO 2016.02 release also is now fully supported on Windows 10 and adds a new debugger tool.… Read More

Posted on

Aldec reprograms HES7 for AXI4 speed

Aldec reprograms HES7 for AXI4 speed
by Don Dingee on 02-26-2016 at 4:00 pm
Categories: Aldec, EDA, FPGA, Prototyping

FPGA-based prototyping firms are all grappling with the problem of higher speed connectivity between a development host and their hardware. Aldec is announcing their solution at DVCon 2016, turning to an AMBA AXI4 interface bridged into a host with PCIe x8.

Faster host interfaces deliver dual benefits in FPGA-based prototyping.… Read More

Posted on

Updated tool cuts through DO-254 V&V chaos

Updated tool cuts through DO-254 V&V chaos
by Don Dingee on 02-03-2016 at 4:00 pm
Categories: Aldec, EDA, FPGA

Audits. The mere mention of the word keeps project managers up at night and sends most designers running. However, in the case of FPGA designs seeking DO-254 compliance, the product doesn’t ship until the audit is complete – there is no avoiding it, or skating around it.… Read More

Posted on

Aldec updates two EDA product lines

Aldec updates two EDA product lines
by Don Dingee on 08-12-2015 at 4:00 pm
Categories: Aldec, EDA

Continuous, incremental improvement based on customer feedback and insight from researchers is a pillar of the Aldec EDA strategy. Within the last two weeks, two of the Aldec product lines – Riviera-PRO, and ALINT-PRO-CDC – have seen new version releases. Here’s a quick look at some of the highlights of both.

Riviera-PRO 2015.06… Read More

Posted on

Aldec packs 6 UltraScale parts on HES-7

Aldec packs 6 UltraScale parts on HES-7
by Don Dingee on 06-01-2015 at 12:00 pm
Categories: Aldec, EDA, FPGA

A few months ago, when the Xilinx UltraScale VU440 FPGA began shipping, one of the immediate claims was a quad-FPGA-based prototyping board touted as “Godzilla’s Butcher on Steroids”. That was a refreshing and creative PR approach, frankly. I’m always careful with less creative terms like “world’s biggest” or “world’s fastest”,… Read More

Posted on

How many coats cover this SoC?

How many coats cover this SoC?
by Don Dingee on 03-11-2015 at 7:00 pm
Categories: Aldec, EDA

“Most interior paint covers with one coat.” Back when there was something called a newspaper, this was an actual blurb in the home improvement pages, section 3, part 8, page 5 of the Chicago Tribune on Sunday, August 13, 1961. Even then, marketers were catering to consumers looking to cut corners and save time, and one-coat coverage… Read More

Posted on

Writing the unwritten rules with ALINT-PRO-CDC

Writing the unwritten rules with ALINT-PRO-CDC
by Don Dingee on 02-09-2015 at 11:30 am
Categories: Aldec, EDA

EDA verification tools generally do a great job of analyzing the written rules in digital design. Clock domain crossings (CDCs) are more like those unwritten rules in baseball; whether or not you have a problem remains indefinite until later, when retaliation can come swiftly out of nowhere.

Rarely as overt or dramatic as a bench-clearing… Read More