Flex Logix has been heads-down for the last several months working toward customer implementations of their EFLX reconfigurable RTL IP cores. Today, they’ve announced a family of 10 hard IP cores ready in TSMC 40ULP, and provided an update to their roadmap for us.… Read More
Author: Don Dingee
Flex Logix validating EFLX on TSMC 40ULP
Striving for one code base in accelerated testbenches
Teams buy HDL simulation for best bang for the buck. Teams buy hardware emulation for the speed. We’ve talked previously about SCE-MI transactors as a standardized vehicle to connect the two approaches to get the benefits of both in an accelerated testbench – what else should be accounted for?… Read More
Customized PMICs with OTP in automotive and IoT
Power. Every device needs it. Managing it properly can make all the difference between a device people enjoy using and one that is more hassle than it is worth. What happens between the battery and the processor is the job of the power management integrated circuit (PMIC).
Why are PMICs gaining so much attention? Increased power … Read More
ARM gets wider and more flexible in vectors
ARM has a storied history of announcing major architecture changes at conferences far in advance of product implementations to get their ecosystem moving. At Hot Chips 2016, their sights are set on revamping the ARMv8-A architecture for a new generation of server and high-performance computing parallelism with a preview of … Read More
More on HAPS hybrid prototyping for ARMv8 with Linaro
A few weeks ago we previewed a Synopsys webinar describing how they are linking the ARM Juno Development Platform with the HAPS-80 and HAPS ProtoCompiler environment. I’ve had a look at the archived event and have some additional thoughts.… Read More
If an Intel 10nm transistor fell in the ARM forest
Intel’s news at IDF this week about partnering with ARM for foundry services on 10nm set off some wild speculation. It’s not a surprise that ARM would enable Intel – they’ve worked together before, ARM is an equal opportunity ecosystem partner, and ARM has publicly announced 10nm cores taped out at TSMC.… Read More
Optimization and verification wins in IoT designs
Designers tend to put tons of energy into pre-silicon verification of SoCs, with millions of dollars on the line if a piece of silicon fails due to a design flaw. Are programmable logic designers, particularly those working with an SoC such as the Xilinx Zynq, flirting with danger by not putting enough effort into verification?… Read More
Semi execs look at IoT tradeoffs a bit differently
What happens when you get a panel of four executives together with an industry-leading journalist to discuss tradeoffs in IoT designs? After the obligatory introductions, Ed Sperling took this group into questions on power, performance, and integration.… Read More
Memory War Z: Samsung spins antidote to 3D XPoint
The 2016 edition of the Flash Memory Summit produced more than the usual amount of excitement. Samsung’s response to the Intel/Micron 3D XPoint challenge arrived in new slideware, indicating the war for next-generation SSDs is just starting. Who has the advantage?
We’d all like to think this is about creating a breakthrough technology,… Read More
Webinar Alert – Helping Mixed Signal not be Mixed Up
Today’s profound statement: “don’t fall in love with your tools, figure out the biz process change first.” Mixed-signal SoC designers are having ample challenges with their design process and are in need of design management, but don’t want another tool to do it.… Read More
Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet