28nm FD-SOI: A Unique Sweet Spot Poised to Grow

I have been silently watching STMicroelectronics pursuing FD-SOI technology since quite a few years. FinFET was anyway getting more attention in the semiconductor industry because of several factors involved. But from a technology as well as economic perspective there are many plus points with FD-SOI. I remember my debate, two years ago, with an IP provider for choosing between FD-SOI and FinFET for some of his IP blocks. Although we were more positive towards FD-SOI the debate was inconclusive at that time, but today the 28nm FD-SOI technology node stands to win as the best value added proposition for the emerging markets such as IoT, automotive, consumer, mobile, and so on. To expand the FD-SOI technology ST has also signed strategic licensing of their 28nm FD-SOI technology with other foundries including Samsung and GLOBALFOUNDRIES. Samsung entered into licensing agreement with ST for manufacturing collaboration on 28nm FD-SOI in mid 2014.

The industry leaders including ST are looking at scaling down the FD-SOI technology to 20nm and even 14nm to gain FinFET like performance at lower power and cost. GLOBALFOUNDRIES has already announced the availability of their own FD-SOI technology at 22nm (the 22FDX platform). In the near future we can see more development on this technology front. How’s the technology poised to provide high-performance and low-power at a low cost? I investigated in detail in a whitepaper at ST’s website.

This is an image from STMicroelectronics showing the flexibility of 28nm FD-SOI technology to modulate the effective channel length of transistors with the same abstract. The leakage current is reduced by an order of magnitude through poly-biasing. There is no junction leakage in this technology.

A single 28nm FD-SOI technology node provides a wide range of operating voltages between 0.6V and 1.1V for trade-off between power and performance. Specialized multi-threshold-voltage (V[SUB]T[/SUB]) libraries such as RVT (Regular V[SUB]T[/SUB]) and LVT (Low V[SUB]T[/SUB] ) are available.

Major EDA / IP vendors have included support of FD-SOI technology in their design flow and availability of IP on FD-SOI. Last year Cadence announced availability of IP solutions on 28nm FD-SOI process. This year Synopsys announced support of FD-SOI technology in their Lynx Design System. Mentor supports FD-SOI process in their tools and design flow as well. There are many others looking up at FD-SOI technology.

A powerful mechanism in FD-SOI technology is body-biasing (enabled in ST’s 28nm FD-SOI technology) with extremely thin buried oxide (BOX) for controlling the channel to further boost the performance or lower the power. The biasing can be modulated dynamically over a wide range during the transistor operation.

The body-biasing provides additional benefits in process compensation. In the above graph, the worst case (WC) performance trend is built using slowest (SS) and leakiest (FF) process corners. With body-biasing the SS and FF process spreads are masked together, thereby recovering performance by 17% without any dynamic power penalty.

The FD-SOI is a planar technology, simple to process at significantly lesser cost, without channel doping, and without much process variation as seen in FinFET technology. There are fewer mask layers and fewer immersion litho layers compared to FinFET technology.

ST’s standard-cell libraries based on FD-SOI technology are optimized for mainstream, low-power and high-performance applications and come in different flavours. There are mask programmable ECO cells which can be used to implement changes by changing metal layers only without the need for full mask-set reorder, thus reducing implementation time and cost. One can choose between 12-track high-performance and 8-track high-density architectures to optimize the PPA (Power, Performance and Area).

There is a wide variety of flip-flops that enable designers to choose the appropriate ones for right trade-off in their designs. Also, there are innovative multi-bit flip-flops to reduce clock-tree load and thus overall dynamic power. The leakage power is also reduced due to sharing of clock inverters between these multi-bit flip-flops. There are multi-stage synchronizers to mitigate the effects of metastability in multiple clock domains circuits.

There is a whitepaperat ST website written by N Shivaram Venkatesh and Bedanta Choudhury. Read this whitepaper to know more details about ST’s offering of standard cell libraries with FD-SOI technology for modern SoC applications. The document also provides benchmarks of 28nm FD-SOI 8T technology against other similar HKMG external references.

The SoCs are dominated by standard cells as they occupy more than half of the area, consuming almost 3/4[SUP]th[/SUP] of total power, and falling in 3/4[SUP]th[/SUP] of the critical paths on the chip. So, it’s essential that standard cells are optimized for PPA in order to optimize the SoC.The FD-SOI technology is in a sweet spot from where it can provide differentiated PPAs for different market segments.For example, ultra-low-power and ultra-low-leakage libraries can be used in IoT and wearable devices; low-power, low-costlibraries can be used in RF analog transmission, a key requirement for smartphones and network applications.

Also read this articleon the CEA-Leti’s announcement of “Silicon Impulse”, a platform to support and broaden the use of FD-SOI technology.

GLOBALFOUNDRIES announcement for support of FD-SOI at 22nm is HERE
Samsung announcement of licensing ST’s 28nm FD-SOI process is HERE