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UTBB FDSOI Devices Featuring 20nm Gate Length

UTBB FDSOI Devices Featuring 20nm Gate Length
by Eric Esteve on 01-09-2014 at 10:33 am

Did you go to IEDM 2013 in Washington DC ? You may have attended to the “Advanced CMOS Technology Platform” chaired by TSMC, and listen to the FD-SOI related presentation “High Performance UTBB FDSOI Devices Featuring 20nm Gate Length for 14nm Node and Beyond”. According with the abstract, this paper is the first time report of “high performance Ultra-thin Body and Box (UTBB) FDSOI devices with a gate length (LG) of 20nm and BOX thickness (TBOX) of 25nm, featuring dual channel FETs (Si channel NFET and compressively strained SiGe channel PFET).” If you didn’t go to Washington DC, or not familiar with FD-SOI, having a look at FD-SOI device architecture could help:

(The readers familiar with CMOS device architecture may prefer to skip this paragraph)

The 20nm Gate Length (L[SUB]G[/SUB]) is the drawn gate feature (L[SUB]EFF[/SUB] being the effective Source to Drain distance, between the two arrows on the picture), and the BOX Thickness (TBOX) is the height of the green Buried Oxide zone, giving to FD-SOI the SOI part of the name: Silicon On Insulator, by opposition to Bulk technology, where there is no green zone, but the Silicon substrate. Another precision can be useful: although the paper mentions 20nm Gate Length, it applies to 14nm Node… That’s just the marketing magic! When you draw a 20nm Gate, the effective distance between drain to Source tend to be smaller, due to chemical effect during Drain and Source doping diffusion, and the Semiconductor industry tend to use this effective channel length as the Node denomination. In this case, everybody knows that smaller is better! These few precisions are for those who are not familiar with transistor architecture (or who may have forgotten that they learn at the University…like me).

The paper (from STMicroelectronics, CEA-LETI, IBM, Renesas, SOITEC and GLOBALFOUNDRIES) can be read here.

Now, we have some basic technology knowledge and we can go further in the paper, and learn more about UTBB FDSOI devices featuring 20nm gate length for 14nm Node:

  • Using FD-SOI allows reaching competitive effective current (Ieff) in comparison with bulk technology, see Fig 3 and 4 above

  • Excellent electrostatics is obtained (Fig 5 to 7 above), demonstrating the scalability of these devices to14nm and beyond. To really understand the above curve, we need to know what DIBL is. From Wikipedia, Drain-induced barrier lowering or DIBL is a short-channel effect in MOSFETs referring originally to a reduction of threshold voltage of the transistor at higher drain voltages. In a classic planar field-effect transistor with a long channel, the bottleneck in channel formation occurs far enough from the drain contact that it is electrostatically shielded from the drain by the combination of the substrate and gate, and so classically the threshold voltage was independent of drain voltage. In short-channel devices this is no longer true: The drain is close enough to gate the channel, and so a high drain voltage can open the bottleneck and turn on the transistor prematurely.

  • Very low AVt (1.3mV•μm) of channel SiGe (cSiGe) PFET devices is reported for the first time. This low Avt is evidence of well-controlled SiGe epitaxy and condensation processes used to form the undoped channel. In other words, that UTBB FDSOI technology manufacturing process can be well managed, from and industry perspective.

  • Bias Temperature Instability (BTI) is improved >20% vs a comparable bulk device and evidence of continued scalability beyond 14nm is provided. This 20% improvement is illustrated in Fig. 14, and demonstrates that UTBB devices show superior reliability to bulk devices. This improvement is attributed to the un-doped channel, and the lower electric fields for the UTBB devices.

The paper ends with scaling considerations: scaling to 10nm node and below will likely require further LG reduction, and to maintain electrostatic performance, a thinner channel thickness (TSi) will also be needed. However, at very thin TSi (< 3nm), quantum confinement starts to dominate Vt. Fortunately, UTBB devices have another scaling enabler: TBOX. Fig. 18 shows DIBL & SS as a function of TBOX. A DIBL reduction of 20mV is seen when scaling TBOX from 25nm to 10nm:

In summary, FDSOI exhibits competitive effective current, excellent electrostatic behavior, very low Avt and Bias Temperature instability 20% better than bulk. Moreover, UTBB FDSOI is planar and capable of 14nm and beyond, at probably a lower cost than FinFET on bulk technology, the latest being more complicated (more expansive?) to process. But such a smart technology will be effectively more cost effective for chip maker if market adoption is wide enough to first benefit from cost reduction linked with volume production, and also large enough IP ecosystem…

From Eric Esteve from IPNEST

More Articles by Eric Esteve …..

lang: en_US

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