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May 19, 2015

Ten Things to Do in San Francisco the Way the Locals Do

Ten Things to Do in San Francisco the Way the Locals Do
by Paul McLellan on 05-19-2015 at 7:00 am
Categories: Events

DAC is in San Francisco, of course, and perhaps you have a day or two to do explore the city. Guidebooks will tell you to visit most of these places but there are much better ways to see them than they typically recommend. Follow these instructions and pretend you are a local.

1. Ride a Cable Car. But don’t wait in line for 45 minutes at Union Square or Fisherman’s Wharf like you are a tourist. Instead, go to the cable car barn on the corner of Washington and Mason. This where the whole system is driven from and you can watch the motors hauling the miles of cable under the streets. And then when you have finished, you can just get on a cable car without needing to stand in line, and go back downtown (or to Fisherman’s Wharf, if you insist). Be like a local and stand on the outside and hang on.

2. See Chinatown. Here’s the best way to do it. Go to Union Square. Go shopping if that’s your thing. Then leave Union Square on Stockton Street and walk through the Stockton Street Tunnel. When you come out at the other end you are in the back of Chinatown and it is like you have landed in another country. Stockton Street is the non-touristy part of Chinatown, full of food shops and the like. Go down the hill one block to Grant Street if you feel the need to buy the sort of things tourists like to buy in Chinatown. Or walk up Washington Street to the cable car barn and ride the cable car back down without standing in line. See the above paragraph.

3. Get a tour to Alcatraz. Warning: you must book well in advance. You will not get tickets if you just show up. Or be like a local and book the night tour, which leaves around 6 and gets back around 9. There are fewer people on the island and you get to watch the sun set through the Golden Gate. The ferry leaves from pier 33. You buy tickets online.

4. See the Golden Gate Bridge. The best way is to rent a bicycle and cycle over the bridge (no toll). There are lots of places on that side of the city that will rent you a bike (if you were a local you would already own one). You can then go down the hill into Sausalito. There is a scheduled ferry back from Sausalito to San Francisco and you can take your bike on it.

5. Take a Tour of the Bay but ignore the official tours of the bay. Just take the ferry to Sausalito (from the Ferry Building or from pier 41), have a drink on the boat, and get the ferry back. Cheapest bay tour available and voted the #2 most exciting ferry ride in the world by the Association of American Travel Writers (the Star Ferry from Kowloon to Hong Kong is #1, so rather a long way to go and imho rather less impressive). Or cycle across the bridge and get this ferry back, see the above paragraph.

6. Walk around Golden Gate Park. The most interesting things are the Conservatory of Flowers, the de Young Museum (closed on Monday) and the Japanese Gardens and tea room. The California Academy of Sciences is also in the park but at $35 entry per adult it is very pricey. If you are feeling like a long walk and have lots of time, walk all the way to Ocean Beach.

7. The Exploratorium is the original hands-on science museum. It has moved and it is now on Pier 15. I’m sure you have heard of it already. Almost anyone attending DAC would find it interesting despite it being somewhat centered on science education of children. In its new location it is just a ten or fifteen minute walk from Moscone or pick up the F-line on market street and ride an historic streetcar too.

8. Go for a rum drink at Smuggler’s Cove. It is at 650 Gough Street. Make sure to take the address or you will walk past it since there is no real sign. Look for red and green navigation lights. The highest rated bar in San Francisco (#16 in the world), 400 rums and over 100 different rum-based cocktails. It is a small tiki bar, so go early to avoid standing in line.

9. Get around town the way the locals do and use Uber. Or Lyft or Sidecar. Just download the apps to your smartphone and you are set to go. Alternatively, if you are feeling sorry for the real taxis, use Flywheel on your phone instead of standing beside the road hoping to see an empty one.

Number 10 would be going to see the Giants baseball but I’m afraid they are on the east coast the entire week of DAC so you can’t. Or the San Francisco Museum of Modern Art (SFMOMA) but that is closed until next year for construction. So the last minute substitute into the rotation will have to be Yerba Buena Gardens.It is just a few steps from Moscone. In fact, it is on top of the North Hall of Moscone (DAC will be in the South Hall). Five acres of public park filled with sculpture, in the heart of the city. Bordering it are a couple of art galleries and the Jewish Museum. There is even a bowling alley.

And if you are a local yourself, feel free to add other ideas in the comments.

May 18, 2015

SemiWiki at #52DAC: Nominated for Best Paper Award!

SemiWiki at #52DAC: Nominated for Best Paper Award!
by Eric Esteve on 05-18-2015 at 7:00 pm
Categories: Events, IP, Sonics

Blogging for Semiwiki is a very good exercise to prepare a paper submission at DAC. Writing a short article using about 600 words to pass one message, and try to deliver this message as clearly as possible. Writing a paper for DAC is very similar, as you have to be synthetic and develop a thesis in 5 slides, no more, as it’s a time limited exercise: 13 minutes to give the complete presentation plus 1 minute for wrap-up. This paper was my very first submission to the Design Automation Conference… but not really the first in semiconductor related conference. I still remember my intense emotion when my first paper was accepted, it was the “3[SUP]rd[/SUP] Multilevel Interconnect Conference”, already in the Silicon Valley (Santa Clara), but it was in… 1986! By the way, the “MIPI Beyond Mobile” paper was nominated by the Designer Track Technical Program Committee as a DAC Best Paper Candidate!

I am certainly proud about this nomination, but it could be a good idea to look at the other five nominated papers in competition (listed by order of appearance) …

In Low Power IP track: “Taking Advantage of the Dark Silicon Opportunity”, by “Drew Wingards” from Sonics. The Semiwiki readers who are familiar with my blogs have certainly noticed that I frequently put the focus on low power design. Moore’s law is what it is (maybe not dead but certainly facing very strong challenges in term of chip cost and power dissipation) and I think that power efficiencywill be mandatory to design future’s chips. In fact to design today’s chip! Using Network-on-Chip (NoC) or Chip Fabric (whatever you name it) to manage not only chip interconnects but also power dissipation in the different blocks looks to be a very good idea. If you want to increase SoC’s power efficiency, you need to partition the SoC in respect with the different functionalities, create specific blocks and manage these from a power perspective… The paper looks attractive; it’s certainly a good candidate!

Still in Low Power IP track: “Techniques for Power and IR Drop Optimization in Sensor Digital IP”, by Aditya Mukherjee from Microsoft Corporation. Even if the sensor market is still a small part of the semiconductor market with $5.7 billion in 2014 (or less than 2% of the total semi market), it’s an essential piece of today’s mobile market and future’s IoT (many) market. It will be interesting to see how Microsoft is dealing with the sensor as a digital IP product…

Before being implemented into a chip an IP stays virtual… No doubt that “IP implementation” is a very important track! Another nominated Best Paper comes from this track: “Effective Analysis and Optimization of On-Chip POP Package Co-Design, for DDR Interfaces”, authored by several people from Broadcom, presented by Chakrapal Kalwa. If you read me you know that I am spending effort on the Interface IP market analysis, and that DDR IP is the largest IP segment. Listening from Broadcom’s experience about Package-on-Package (POP) implementation of a DDR interface is certainly a must do!

In Subsystem IP & IP integration track, this paper “Design in the Eye of the Hurricane – Building Optimal Vision Subsystem” from Cadence Design Systems, presented by Chris Rowen is the 4[SUP]th[/SUP] nominated for Best Paper Award. Also a must attend paper! Martin Lund came from Broadcom in 2012 to manage Cadence’s IP business and it took only two years for Martin to make acquisitions (Cosmic Circuit, Evatronix or Tensilica) and boost Cadence’s IP business and position the company as the #2 just behind ARM for processor (and DSP) IP! I would guess that this subsystem is built around a Tensilica processor core… Certainly a good candidate for the Best Paper Award.

The last nominated paper comes from the Verification IP track: “Why Testbench Should Control Processor Execution: a Novel Approach to Bridge the Gap Between IP and SoC Verification” presented by Ritesh Agrawal from Freescale Semiconductor. If I understand well, the idea is to use the Verification IP to check for the IP and take the opportunity to verify the complete SoC as well. This is certainly a hot topic as today’s chip design is under the highest ever TTM pressure. The challenge will probably to clearly explain this complex topic in 13 minutes!

The reader may think that I am afraid of this strong competition, and I must recognize that these entire papers look very attractive as each of these are dealing with a crucial part of the chip design. But, as we say in French “A vaincre sans peril, on triomphe sans gloire” (in “Le Cid” from Corneille in the XVII century). To be honest, I still think that I keep a chance. In fact, I spent more than 6 weeks working full time to analyze the MIPI Ecosystem a couple of months ago before writing this paper, and I have made two presentations at the MIPI Face to Face meeting in Seattle (so I could fine tune the analysis, thanks to the critical review from MIPI technology experts…).

I have created a specific tool to analyze this ecosystem in 2015, compare it with 2012 (see this example of MIPI specification support by IP vendors evolution between 2012 and 2015 on the above picture) and scientifically derive trends about MIPI technology pervasion in emerging systems like wearable or IoT in the future. Such analysis aiming to be used by IP vendors to focus on the MIPI interface specifications which will be effectively used “beyond mobile” in the future!

From Eric Esteve from IPNEST

May 18, 2015

S2C’s Virtex UltraScale Prototyping Provides Designers Much Needed Flexibility

S2C’s Virtex UltraScale Prototyping Provides Designers Much Needed Flexibility
by Majeed Ahmad on 05-18-2015 at 12:00 pm
Categories: EDA, FPGA, S2C EDA

The advent of large system-on-chip (SoC) designs has brought FPGA prototyping hardware into the limelight and the launch of S2C Inc.’s Single VU440 Prodigy Logic Module just shows how far off-the-shelf prototyping has come in a bid to complement hardware verification and software development. Hardware verification and software development tasks like OS integration and apps testing are two fundamental considerations in the mega-million-gate SoC designs from a cost standpoint.

The San Jose, California–based FPGA prototyping solution provider has released the Single VU440 Prodigy Logic Module that will support the latest Xilinx Virtex UltraScale 440 FPGA. Xilinx Virtex UltraScale VU440 is a 4 million logic cell programmable device that is equivalent to over 50 million “equivalent ASIC” logic gates. The Xilinx FPGA enables multicore prototyping of even the most advanced ARMv8-A architectures and thus can accelerate time-to-market for powerful SoC designs.

Xilinx Virtex UltraScale 440 FPGA allows multicore prototyping

S2C’s Single VU440 Prodigy FPGA prototyping board for Xilinx Virtex UltraScale 440 FPGAs comes in a small form factor of 260 x 170mm and offers a number of add-on features. Moreover, it includes the Prodigy Player Pro Runtime Software feature that can be run on both Windows and Linux computers to perform basic functions such as FPGA download, write/read on-board SD card for off-line download, clock and reset set-up, I/O voltage settings, hardware monitoring and self-test.

S2C’s new offering—fully integrated into the company’s Prodigy Complete Prototyping Platform—displays a modular approach for managing the boards and design teams remotely via the cloud. The product showcases three prominent highlights that affirm S2C’s claim of offering a complete prototyping platform: capacity, high-speed interfaces and enterprise-level could access.

SoC Design in the Cloud

S2C is probably the first company to take FPGA-based prototyping system to the cloud and its enterprise cloud access service is aimed to facilitate collaboration among geographically distributed SoC design teams, third-party IP vendors and foundry partners. The company’s prototyping system with cloud-based access works through both Ethernet and USB links to enable remote management capabilities. The ability to download FPGAs remotely allows chip designers to reconfigure SoC at any stage of the design flow.

Cloud Cube is a multi-purpose platform for managing large SoC configurations

S2C’s Single VU440 Prodigy Logic Module can be used in standalone or Cloud Cube enterprise modes. Cloud Cube is the company’s enterprise-class prototyping system for supporting large-scale SoC designs. It allows up to 16 Single VU440 Prodigy Logic Modules to be configured in the cloud.

Memory and Gate-level Capacity

Sufficient memory and gate-level capacity are crucial in prototyping large and complex SoC designs where the number of processors and communication interfaces is constantly growing to keep up with system functionality. Single VU440 Prodigy Logic Module is twice as much dense than its predecessor—V7 Prodigy Logic Modules series—and boasts 20 percent more I/Os compared to the V7 series. Moreover, multiple Single VU Logic Modules can be conveniently connected together to expand the FPGA-based prototyping system capacity.

The growing number of SoC cores and peripherals demand more capacity and memory

Then, there are add-ons like DDR4 modules that can quickly create systems with multi-gigabyte memories and thus facilitate scalability and extensibility of the FPGA-based prototyping system. Released in 2014, DDR4 is one of the latest variants of DRAM memory and is faster than DDR2 and DDR3 technologies. The features such as DDR4 allow peripherals and processors on daughter cards to add various IP functionalities.

High-speed Interfaces

The next key highlight in the evolution of FPGA prototyping alongside the SoC rollercoaster is speed. Although, large FPGAs like Xilinx Virtex UltraScale VU440 have eased the design partitioning challenge, these devices come with large pin-outs that lead to big PCBs with a high number of interconnects. That leads to issues like signal routing, capacitive loading and impedance matching, which in turn, can slow down the prototype run.

So it’s imperative that large prototype boards allow modular implementations and accommodate high speeds. S2C’s Single VU440 Prodigy Logic Module provides eight general-purpose connectors for a variety of system interfaces and two GT connectors for high-speed serial connectivity. It comes with a built-in PCIe3 support for high-speed interfaces that run in the GHz range.

FPGA prototype board supports high-speed interfaces

S2C’s prototyping board also features Player Pro Runtime Software that supports Virtual SWs & LEDs for simple tasks such as changing a setting or indicating a condition remotely. Furthermore, it automatically determines what daughter cards are installed on Logic Modules or cable setups between connectors.

Also read:

A Brief History of S2C: A Vision for FPGA Prototyping Realized

S2C eyeing 1B gate FPGA-based prototypes

Breaking the SoC lab walls

Majeed Ahmad is the former Editor-in-Chief of EE Times Asia and is author of six books about electronics industry.

May 18, 2015

FD-SOI the Synapse Way

FD-SOI the Synapse Way
by Paul McLellan on 05-18-2015 at 7:00 am
Categories: FD-SOI, Foundries, STMicroelectronics

Last week I talked to Marco Brambilla of Synapse Design. Synapse is a design services company headquartered in Silicon Valley. It was founded in 2003 by Satish Bagalkotkar and has been profitable since the beginning. Today it has over 700 people. In addition to the headquarters in Santa Clara, they have a software group in Colorado, and design centers in Shanghai, Bangalore, Taiwan, Italy and more. They are a pure design services company. While most of their projects are some version of ASIC, Synapse engagement models also include customer-provided RTL and Synapse completes the design tapeout, or a full turnkey starting from architecture or specification down to design tapeout.

As you might guess from his name, Marco is Italian. But he works in Santa Clara today, having relocated to the US from one of Synapse’s European sites in Grenoble. Prior to that he worked for ST Microelectronics for a decade in both the US and Italy (and short stays in several other countries). Marco is a director of engineering at Synapse but he is also their resident expert on FD-SOI design, given his long history at ST.

In 2012 Synapse worked on a mobile chip and he thinks that this is the first FD-SOI production ASIC. They worked closely with ST since they were blazing a trail and helping to mature the design flows. Since then they have taped out another 3 or 4 chips that are in production, in both mobile and networking. All these chips involve aggressive power management with multiple power domains and all the tricks that used to be esoteric and are now mainstream.
One of the things that FD-SOI brings that is not available in FinFET is the capability to back-bias which can be used in a number of different ways, either to increase performance or to reduce power (especially leakage). I asked Marco if they had used it. He said that on the first modem chip they had indeed used it in order to get the performance up, but they had not used it on the networking chips. It is not yet a mature technology and use requires significant involvement of the foundry (today ST and Samsung have announced availability).

Currently Synapse are close to taping out a chip for a machine-to-machine communication (IoT) device. A portion of the chip is always-on. The rest of the chip spends a lot of its time powered down with just retention registers holding values for when everything gets reactivated. They even include an embedded PCM (process control monitor) to really measure accurately the PVT conditions during use. Their plan of record is to use back-biasing to keep leakage very low and they are in discussions with ST about the details. The usage of back-biasing is not yet completely turnkey. The effect for the designer is largely that it removes the slow corner and adds a few more timing corners that need to be checked. But there are already lots of timing corners at 28nm and below, so this is not a lot of extra work. However, once a back-biased design goes into production, a few samples are required and then tuning needs to be done to calibrate exactly how the product behaves. This is especially important when using DVFS (dynamic voltage and frequency scaling). One big challenge is making the biasing temperature independent, something that is a challenge with DVFS no matter what technology is in use.

I asked Marco what was the sweet spot for FD-SOI. Obviously Synapse does designs in lots of other processes including FinFET. He said that the sweet spot is non-extreme-high-performance, not humungous gate counts, where power control is important (is it ever not?). Not the 300-400M gates, but rather the 10-20mm square devices. For consumer devices the mask cost and wafer cost goes down predictably from being a 28nm planar process. It has the buried box but it does not need the masks and process steps for the stress relief used in bulk technologies.

Another advantage is the comparatively wide operating voltage range. On the current chip they started assuming they would use a 40nm low power process and when Marco started talking about 28nm FD-SOI, everyone thought he was crazy. But a small device has very good yields. And whereas at 40LP every foundry only has 1.1V on 28nm FD-SOI can run from 0.8V up to 1.1V. With care in memory choice (or splitting the core from the periphery) the voltage can be reduced even further to 0.65V with obvious savings in power.

There is a perception that ST is a small fab but with Samsung as a partner that is not an issue. Marco told me that they have several customers with active FD-SOI projects and not just with ST.

May 18, 2015March 22, 2022

ClioSoft Celebrates 2014 with 30% Revenue Growth!

ClioSoft Celebrates 2014 with 30% Revenue Growth!
by Daniel Nenni on 05-18-2015 at 1:00 am
Categories: Cliosoft, EDA

One of the first companies we worked with when SemiWiki went live in 2011 was ClioSoft. They had a problem with a competitor spreading misinformation which is certainly not unheard of in EDA. When a company cannot compete technically sometimes they resort to dirty tricks or legal distractions. The first ClioSoft article we published earned more than 7,000 views which was a pretty big number for a brand new website:

“Hardware Configuration Management and why it’s different than Software Configuration Management”

by Daniel Payne
Published on 03-23-2011 12:51 PM
Number of Views: 7073

ClioSoft Analytics:
Total Blogs: 51
Total Views: 150917
Average: 2959

Four years and 51 blogs later we are still working with ClioSoft and it is a pleasure to see their continued success. One thing that you will notice is that quite a few of the blogs are based on customer experiences. ClioSoft gave us access to their customers and they were happy to talk to us. That speaks volumes abut an EDA company. By the way, that 30% growth is revenue, not bookings or some other magical number:

ClioSoft, Inc., a leader in system-on-chip (SoC) design data and intellectual property (IP) management solutions for the semiconductor design industry, today reported a 30% year-to-year increase in revenue for 2014. The rise in revenue is due to increased adoption by new and existing customers. Twenty-five new accounts were added to ClioSoft’s growing customer base, several of which were already existing users of software- based data management solutions that migrated over to ClioSoft’s SOS design data management platform.

“It has been a good year for us” said Srinath Anantharaman, founder and CEO of ClioSoft. “A number of companies have started to standardize on the SOS design management platform as it is the only tool supporting all types of designs – digital, analog, RF and mixed-signal.”

The other thing I wanted to mention is the ClioSoft DAC presence. You can tell a lot about a company by what they do at DAC. Last year ClioSoft had a conservative booth but put on one of the best DAC parties and it was all about thanking customers with good food, excellent wine, and a very nice gift. In fact, ClioSoft sends my family a gift every Christmas, now that is class, absolutely.

About ClioSoft: ClioSoft is the premier developer of hardware configuration management (HCM) solutions for digital, analog, RF and mixed-signal designs. The company’s SOS Design Collaboration Platform is built to handle the complex requirements of system-on-chip design flows. The SOS platform provides a sophisticated multi-site development environment that enables global team collaboration and efficient management of design data from concept through tape-out along with an enterprise IP management and design reuse solution. SOS is integrated with leading design flows –Cadence’s Virtuoso[SUP]®[/SUP] technology, Keysight Technologies’ Advanced Design System (ADS), Mentor Graphic’s Pyxis Custom IC Design, Synopsys’ Galaxy Custom Designer[SUP]®[/SUP] and Laker3™ Custom Design.

Also Read

Secret Sauce for Successful Mixed-signal SoCs

DNA Sequencing Eyes SoCs for Stability and Scale

Make Semiconductor IP Reuse Successful?

May 17, 2015

How Sidense Sees The Smart Connected Universe

How Sidense Sees The Smart Connected Universe
by Tom Simon on 05-17-2015 at 7:00 am
Categories: EDA, General, IoT, IP, Mobile, Sidense

Sidenserecently conducted a webinar on what they call the Smart Connected Universe. They consider the Smart Connected Universe as something that includes a collection of market segments that are both smart and connected. This casts a big net, and includes what many are calling IoT, but goes further into medical, automotive and industrial. While you can quibble about definitions, any way you look at it this is a huge segment that is growing in size and importance. It also imposes a number of design requirements that are new: low power, secure and often operating in challenging environments.

Regardless of how you choose to define things, based on Sidense’s own summary in the webinar, their business is growing – at a 45% compound annual rate. They have about 65 employees and of those 80% are in engineering roles. They have been around for about 10 years and are finding increasing demand coming from all the segments in their Smart Connected Universe.

They chose a couple of specific products to illustrate the utility of their one time programmable (OTP) non-volatile memory (NVM): mobile phones and the automotive market. Sidense asserts that there are up to 20 instances of OTP in a smart phone these days. OTP NVM is used in power management IC’s (PMICS), sensors and for security and DRM. You can see how heavily each of these items is used in smart phone designs.

PMICS are “make or break” technology for mobile phones. They control the utilization of power for the high power RF circuits like PA’s and also handle battery management, which translates into a critical market success factor. OTP NVM is ideal for this application as calibration and trim values can be programmed into the chip on the tester. The long life and high reliability of OTP NVM will ensure long product life.

Automotive IC content is growing even faster than the tablet or mobile phone market. Power management, reliability and security are also just as, if not more, important here too. Engine compartments and car interiors are subject to temperature extremes – hot and cold. Sidense states that automotive electronics make up more that 30% of the production cost of a car.

There are alternative ways to store non volatile data on/in IC’s, but Sidense’s antifuse technology is easy to use because it works on standard digital and analog processes, without the need for additional processing layers or masks. It is also very secure because there are no physically inspectable characteristics that indicate the value of a bit location. Even read voltage monitoring will not reveal data values.

Error correction is available in their memory macros, as well as few times programmable (FTP) emulation. I won’t go into all the details here. The webinar covered their technology in more detail and talked about availability on various fabs and processes.

OTP NVM is a vital link in the Smart Connected Universe. It is providing security and reliability that we likely take for granted. This is something I only gained a true understanding after learning more about its design characteristics and applications.I encourage you to view a replay of this webinar.

May 16, 2015August 22, 2024

ASMC 2015: GlobalFoundries 22nm SOI plans and more!

ASMC 2015: GlobalFoundries 22nm SOI plans and more!
by Scotten Jones on 05-16-2015 at 3:00 pm
Categories: Foundries, GlobalFoundries, TechInsights

The Advance Semiconductor Manufacturing Conference was held on May 3[SUP]rd[/SUP] through May 6[SUP]th[/SUP] in Saratoga Springs, New York. ASMC brings a unique operational perspective to technical conferences related to semiconductors. In this blog I wanted to discuss what I thought was the most interesting paper of the conference, one of the keynotes given by Thomas Caulfield of Global Foundries entitled “Balancing Eco-System Value Creation and Value Capture”

But first I have to admit to a bit of a surprise here, I am generally not a fan of conference keynote addresses because I think they are often attempts to stake out some grand vision that they then fall short of. In this particular case, at least from my perspective there was enough really interesting information in the presentation to make it both interesting and informative.

Megatrends and connectivity
The keynote began with a review of some of the overreaching trends that are driving the semiconductor industry: expanding coverage and bandwidth needs for wireless connectivity, mobile computing and the internet of things driving low power solutions, network and storage backbones driving performance solutions and the need for security.

The evolution of computing was noted to have been driven from wired low bandwidth solutions to high bandwidth solutions leading to the internet of things.

The supply chain ecosystem is approximately $74 billion dollars of equipment and materials suppliers supporting approximately $419 billion dollars of semiconductors and related enterprises supporting approximately $1.55 trillion dollars of electronics.

Innovation benefits and costs
In the fourth installment of my recent series on Moore’s Law I argued that foundries have seen a pause in cost reduction around the 20nm/14nm nodes but that I expected this to be a temporary pause.

Moore’s Law is dead, long live Moore’s Law – part 4

Some other analysts have argued that 28nm is the low point for cost per transistor. In Dr. Caulfield’s slides he shows a pause in cost per transistor reduction at 20nm, he then shows that pause continuing at 14nm for other foundries but that at GlobalFoundries they see a “typical” cost per transistor reduction because of the high density of their 14nm process. Furthermore he is forecasting continued cost per transistor reductions at 10nm and 7nm in-line with our analysis.

GlobalFoundries view is that 28 nm will be a long lived node, 20nm will be a short lived node and 14nm will go on “forever”. 14nm offers “power, performance and cost” and many people are designing out of 28nm into 14nm skipping 20nm.

But there is a cost to these innovations, new materials and masks are rapidly piling up. For example there is a slide in the presentation showing approximately 40 masks at 65nm rising to approximately 57 masks at 28nm and approximately 68 masks at 16nm/14nm. This growth in process complexity drives up costs, reduces yields and increases cycle times. Dr. Caulfield noted that even at 1 day or 0.8 days per mask these processes take a long time to complete. The capital required for these processes are also increasing from around $65 million dollars per thousand wafers out at 65nm to around $100 million dollars for 28nm and around $135 million dollars at 16nm/14nm. The resulting improvements in transistor density are more than offsetting this so far, but the cost of entry is limiting the number of players at the leading edge (more on that below).

Design costs are also rapidly rising from approximately $60 million dollars at 65nm to around $140 million dollars at 28nm and nearly $500 million dollars at 16nm/14nm. Clearly only the highest running parts can provide a reasonable return on such a huge investment.

Consolidation
As noted above the cost of the latest state-of-the-art technologies is growing. At 14nm Dr. Caulfield noted that a $12 billion dollar investment is required to reach a competitive scale.

The rising costs of semiconductor facilities and technologies has driven consolidation to the point that there are now only four companies producing 14nm node logic processes, Global Foundries, Intel, Samsung and TSMC.

Global Foundries locations
With the IBM acquisition, GlobalFoundries now has three global manufacturing clusters, the Northeast tech corridor, Dresden and Singapore.

In the northeast tech corridor GlobalFoundries has the former IBM 200mm fab in Burlington Vermont running RF foundry, the former IBM 300mm fab in East Fishkill running ASICs and Server parts and the Global Foundries 300mm fab in Malta that is the R&D center and does 28nm and smaller manufacturing and is the only Global Foundries location running 14nm.

Dresden is a 300mm fab that originally came from AMD and is now focused on 20nm and larger manufacturing.

Singapore is the former Chartered fab location with 200mm and 300mm fabs. Singapore is the trailing edge manufacturing location for Global Foundries.

Dr. Caulfield offered the opinion that all the semiconductor manufacturing “corridors” that will be built around the world have been built.

During the question and answer session there was a question about labor cost differences around the world. Dr. Caulfield said that labor cost is a pretty small percentage of depreciating cost and he thinks you can innovate around it. Furthermore he said that materials and electric costs are pretty similar around the world. I would interject here that what is not the same around the world are tax policies and the availability of government incentives and these are a significant factor in the overall cost equation.

Collaboration
One of the big points of the presentation was collaboration and the 14nm collaboration between GlobalFoundries and Samsung is clearly a key part of GlobalFoundries strategy. GlobalFoundries has licensed Samsung’s 14nm process and customers will be able to get 14nm wafers on the same process from Global Foundries Fab 8 in Malta NY as well as Samsung’s S1 and S3 fabs in Giheung South Korea and S2 fab in Austin Texas.

Silicon On Insulator (SOI)
During the question and answer session I asked Dr. Caulfield about GlobalFoundries SOI plans. He replied that they are developing a 22nm process in Malta for manufacturing in Dresden. The goal is 14nm FinFET performance at 28nm costs. This would certainly be an interesting process if they can meet that goal. I do worry that GlobalFoundries appears to pursuing a lot of different directions for leading edge processes. IBM has a 14nm FinFET on SOI process with trench DRAM they will presumably have to support for server products, GlobalFoundries and Samsung have a 14nm FinFET on bulk process for general foundry use and GlobalFoundries is now developing a 22nm SOI process. That strikes me as a lot of leading edge processes for one company to support.

Conclusion
Dr. Caulfield sees logic technology continuing down to 3nm with consolidation and ultimately collaboration as key factors.

May 16, 2015

MediaTek Breaks the ‘Core’ Barrier, Again

MediaTek Breaks the ‘Core’ Barrier, Again
by Majeed Ahmad on 05-16-2015 at 7:00 am
Categories: Arm, IP, Mobile

Who says Asian companies can’t innovate? Just look at how Taiwan’s MediaTek Inc. has conceived a 64-bit system-on-chip (SoC) that features 10 Cortex-A cores in a tri-cluster configuration. MediaTek’s Helio X20 processor is also the first mobile SoC that boasts ARM’s latest CPU and GPU cores. Moreover, it sports an ultra-low-power Cortex-M4 core that can be used for always-on sensor functions like gesture recognition.

MediaTek’s deca-core design is arranged in a tri-cluster big.LITTLE setup

MediaTek’s deca-core SoC is based on a unique architecture that goes beyond ARM’s conventional two-cluster big:LITTLE setup and creates extra tiers in the SoC design to further optimize mobile computing tasks. The first CPU cluster in the Helio X20 SoC is dual-core and uses two Cortex-A72 CPUs with a maximum frequency of 2.0GHz to handle the most intensive tasks like gaming.

The other two clusters are quad-core, each using four Cortex-A53 cores, one optimized for high performance at 2GHz frequency while the other optimized for low-power consumption at 1.4GHz frequency. These quad-core clusters will handle light-weight computing tasks such as video playback that remain active for longer periods and require minimal power consumption. MediaTek claims that its new chip will enable 15 percent to 40 percent gain in power consumption compared to the rival chips based on two-cluster big:LITTLE architecture.

MediaTek is also the first chipmaker to officially announce an SoC based on ARM’s Mali T800 series GPU core. The Helio X20 chip sports an ARM Mali-T800 MP4 GPU clocked at 700MHz, and it features 2560×1600 displays, 4K video hardware decode, slow-motion video capture and support for dual-ISP 25-megapixel camera configurations. MediaTek’s new mobile SoC includes a dedicated hardware accelerator for 4K H.265 video decode and encode.

It’s a notable development because the largest silicon vendor from Taiwan hasn’t aimed very high in terms of GPU integration in the past. Moreover, the Helio X20 chipset includes CAT-6 LTE modem that supports 28 LTE bands and 2×20 carrier aggregation.

MediaTek is using auto analogy to promote tri-cluster SoC

MediaTek vs. Qualcomm

The innovative CPU arrangement can transform the Hsinchu, Taiwan–based chipmaker into a serious contender for sockets in premium smartphones and tablets. And it can also set MediaTek squarely against mobile SoC kingpin Qualcomm for another round of mobile processor wars. There is an interesting history between MediaTek and Qualcomm when it comes to adding cores to mobile SoCs.

In summer 2013, MediaTek launched the MT6595 mobile SoC and claimed that it’s the first true octa-core device in the market. At that time, Samsung had already launched the octa-core Exynos chip, but it only activated half of its cores at once, while MediaTek chips could run all eight cores simultaneously. Qualcomm first made fun of MediaTek’s extra cores and called it ‘dumb.’ Then, the San Diego, California–based semiconductor giant followed suit and released its own octa-core mobile SoC, the Snapdragon 615.

Helio X20 supports up to 32MP or dual 13MP cameras

Taiwan’s SoC powerhouse has raised the mobile chipset bar again, and it’s yet to be seen how Qualcomm and other leading mobile SoC makers respond to this aggressive move. However, for MediaTek, it cuts both ways. The powerful new chip can give MediaTek a strong foothold in the mid- to high-end smartphone and tablet markets. On the other hand, the chipmaker from Hsinchu has set itself for a giant challenge of getting three clusters work seamlessly and keep power management subsystems in control.

The Helio X20 chip, built on 20nm manufacturing process, is expected to be released in December 2015. It’s likely to be shipped in the first quarter of 2016.

Analog Market Leaders Eyeing on IoT Applications

Analog Market Leaders Eyeing on IoT Applications
by Pawan Fangaria on 05-15-2015 at 12:00 pm
Categories: EDA, Foundries, IoT

When we talk about analog IC market, one can easily guess who the leader with lion’s share in the market is. There are also next level leaders with impressive growth rates in this market. The analog market as such is poised to grow with Internet of Things (IoT) because it supplies some of the key components such as data converters, op amps, analog switches, audio amplifiers, and so on for IoT segments like wearable, home, automotive, industrial etc. Therefore it is interesting to watch the activities of upcoming leaders and the top leader on how they avail the opportunities presented by the IoT wave.

While there is not much change in relative ranking of top10 analog IC leaders between 2013 and 2014, the growth data of a few companies indicate that they are well established to benefit from the developing IoT ecosystem. Let’s look at the table below –

Texas Instruments(TI) is the clear leader, much ahead from the rest. Also, it has posted a decent 13% growth in sales with current market share at 18%. The analog IC market has been perceived to be fragmented and a market share of 18% may look small for TI; however it’s about 3 times the market share of each of its nearest four rivals. ST Microelectronics, Infineon, Analog Devices and Skyworks Solutions are each at 6% market share with revenue nearly 1/3[SUP]rd[/SUP] of TI.

As I have said earlier in one of my blogs on TI, analog and embedded are their core strengths. Their strategy is to concentrate on analog and embedded market and eventually win in the IoT space. The Apple watch, launched recently contains Opp Amp, OPA2376 from TI. TI gets 62% of its total revenue from analog IC sales. In sensors space also TI improved its rank from 3[SUP]rd[/SUP] in 2013 to 2[SUP]nd[/SUP] in 2014, first being Bosch. TI’s focus on analog market has been there since long. It became the first manufacture of analog devices on 300mm wafers after acquisition of 300mm manufacturing tools from Quimonda in 2009. TI acquired two more fabs in 2010, one from Spansion in Japan and the other from Censon in China; both of these manufacture analog ICs. Then in 2011, TI acquired National Semiconductor, a leader in analog market. TI aims to reduce its chip manufacturing cost by up to 40% by moving the manufacturing to 300mm wafers.

Skyworks Solutionsshowed dramatic improvement from 2013 with a 42% jump in sales and improving its rank to 5[SUP]th[/SUP]. Skyworks supplies analog and mixed-signal components to top smartphone and mobile devices companies including Apple and Samsung. The iPhone 6 has many amplifier components from Skyworks. Also, Skyworks’ wireless technology can be found in General Electric healthcare equipments. Recently Skyworks begged a deal from Panasonic to supply high-performance filters. Skyworks is aiming high to become a prime supplier for automotive, home, consumer electronics, and wearable segments of IoT market. The rapid rise of Skyworks can help it climb higher ranks in the analog space.

Although ST’s sales in analog increased just by 2%, its market share must improve in future as it has started supplying gyroscopes and accelerometers for Apple watches. NXP’s analog sales also increased substantially by 21%; however NXP has a market share of just 4% in analog ICs.

Analog Devices (ADI) analog IC sales increased by 9% compared to 2013. It’s worth mentioning that ADI’s touch screen controller (with 3D/Force Touch feature) has found its place in Apple watch. It’s expected to get into iPhone 6 and next generation iPad as well.

A detailed report about the market share of top10 analog IC suppliers is available at IC Insights website here. Also read, “Secret of TI’s Success in Analog & Embedded Space”.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

May 15, 2015

EDAC Game of Thrones: Bob Smith is the New Executive Director

EDAC Game of Thrones: Bob Smith is the New Executive Director
by Paul McLellan on 05-15-2015 at 7:00 am
Categories: EDA, General, IP

Bob Smith has been appointed executive director of EDAC, following the retirement of Bob Gardner after nearly 20 years. Bob (Smith) was most recently the marketing and business development VP for Uniquify. However, he has been in the industry for a long time with stints at IKOS, Synopsys, LogicVision and Magma. He has even been to one more DAC than I have. So now he gets to sit on the iron throne of semiconductor design.

Yesterday I talked to him. The first thing I asked was why he took the job. He said that it came out of the blue. He has spent most of the last twenty years being involved with smaller companies trying to grow. But the more he thought about EDAC the more interesting the challenge seemed: not a single company but lots of companies with their own issues and agendas. He has now been in the job for just a few days so he is still in discovery mode finding out what EDAC has in motion already, and what the member companies want.

Of course one thing EDAC is heavily involved with is DAC, but that is just a few weeks away so it is like a 747 that is almost up to takeoff speed halfway down the runway. Don’t touch the controls. But it is a great opportunity for Bob to meet all the member companies that are not based in silicon valley since this is the one time each year when pretty much everyone is under one roof.

I asked Bob what he thought the big member companies get out of EDAC. After all, even DAC is of limited impact since they all have their own conferences that they even take on the road to different parts of the world. In his few days in the job he said that two things that the big companies care a lot about (and the smaller ones not so much) are the export committee, which makes sure that the industry presents a united voice to ensure that EDA/IP doesn’t suddenly become subject to burdensome export regulations, and the piracy committee. Everyone has head the stories of how “famous Chinese company X” has thousands of designers but only a dozen copies of some EDA tool. Some of them are even true, at least in the aggregate. The smaller companies have a different set of issues mostly with getting accepted at customers and foundries.

I asked Bob about geographically expanding EDAC’s scope. It seems to be very silicon-valley-centric especially when you compare it to, say, SEMI or GSA which have events all over the world. He agreed. After all, if you look at a heat map of where semiconductor design is done then China lights up bright, and Vietnam seems to be where India was maybe 20 years ago. Taiwan, and to a lesser extent Korea, is the center of the fabless ecosystem. And there is still lots going on in Japan even if the number of companies has reduced significantly through mergers. But EDAC never calls.

Another challenge is to expand EDAC’s scope in general. The organization was created originally by the EDA companies. Back in that era there wasn’t an IP industry to speak of, and the embedded software component of electronic systems was small to non-existent. The reality is that for designing an SoC that EDA is important, but no less so than IP and embedded software. The more security becomes an issue, the more it requires a solution involving both hardware and software and starts to become more of an EDA problem. The more reliability becomes an issue, for automotive and medical for example, the more the type of discipline that we have to use in semiconductor design is required. After all, building a chip is a bit like writing software, but you have to ship the software before you even run it. Taping out a chip is a multi-million dollar bet, so you do everything to tilt the odds in your favor.

Of course IP is hugely important. SoC design is largely about IP assembly with a relatively small percentage of differentiated content. ARM and Sonics are on the board of EDAC but most IP companies (the ones that are not EDA companies too) are not members.

Bob knows that the challenge going forward is to ensure that EDAC delivers value to its members and, ideally, finds a way to broaden its reach to deliver value to companies that are not currently members but which are first-class-citizens in the semiconductor design ecosystem. EDAC has the tag line “where electronics begins” but there are a lot more than silicon-valley EDA companies involved.