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Semiconductor Expert Forum

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Flash Automobiles

Flash Automobiles
by Paul McLellan on 05-22-2015 at 7:00 am
Categories: Foundries, GlobalFoundries

Building flash memory for automotive is not straightforward. Just look at the specs you have to meet for grade 1 qualification:

  • 100,000 cycles of endurance (writing new values)
  • 10 years data retention
  • all at 125°C (also needs to work down to -40°C)

GlobalFoundries have been working with Silicon Storage Technology (which is a wholly-owned subsidiary of Microchip) on non-volatile memory for a decade (that would be longer than GF has been in existence, but Chartered had a long history before they were acquired). They started at 0.35um, then had memories at 0.13um. Now they have announced the latest version in 55nm. The details are that the the two companies:announced the full qualification and availability of SST’s 55nm embedded SuperFlash non-volatile memory on GF’s 55nm Low Power Extended (LPx)/ RF enabled platform. The qualification of GF’s 55nm, split-gate-cell SuperFlash technology-based process was performed according to JEDEC standards. This process technology also met the requirements of AEC-Q100 Grade 1 qualification with an ambient temperature range of -40°C to 125°C, and demonstrated endurance of 100K program/erase cycles with more than 20 years of data retention at 150°C.

So it looks like they are officially qualified at grade 1 but also meet the more stringent requirements of grade 0 (don’t you like the numbering system?) which requires data retention for decades at 150°C.

I had a call earlier in the week with Kevin Yang (who was in Singapore) and Jeff Darrow (on the east coast) of GF, and me, at 7am half-asleep in California. They told me that the bit-cell is tied as the smallest in the industry. The maximum sized macros that they have off-the-shelf is 16Mb (2 megabytes) but there is no fundamental limitation on them going up to 4 megabytes, just that the current target market segments don’t require such large memories. The 55nm process is manufactured in GlobalFoundries’ Singapore facility, I am assuming in fab 7 which is 300mm.

But this non-volatile memory is not just targeted at automotive, it is well-suited to a wide range of applications and they have created a portfolio of macros optimized to different segments such as smartcard, microcontroller, NFC, wearables and IoT. Smartcards in particular are a high-volume user of flash technology although obviously they don’t actually require such high temperature qualification. You want a 125°C credit card in your pocket? I didn’t think so. You probably aren’t going to keep a credit card for decades either.

However, automotive is a big market. According to IHS, the automotive semiconductor market is forecast to reach $31B in 2015, up 7.5% on 2014. Embedded Flash-based semiconductors are a key component of this market segment. For this market the long lifetime and large temperature range is essential. Cars can last at least ten or even twenty years, and they have to work in the middle of winter in Canada and in the middle of summer in Arizona. Data retention (and lots of other things) becomes more of a problem the higher the temperature, and it can get really hot under the hood of a car, so the high temperature is not just an academic number in a SPICE deck but a genuine requirement.

In April, GF also announced a flash memory with NXP based on their 40nm process which will also be manufactured in Singapore. However, this is a collaboration with NXP and is an NXP-specific offering. So while the two offerings both show GF’s ability to bring eNVM to production, the two are complementary.

GF’s 55nm LPx/RF platform, complete with eNVM technology, is available to customers now. Flash cars with flash memories.

The GlobalFoundries website is here.

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Realize the Genius of Your Design!

Realize the Genius of Your Design!
by Daniel Nenni on 05-21-2015 at 1:00 pm
Categories: EDA, FPGA, S2C EDA

I think we can all agree that no matter what you are designing, FPGA prototyping can help. The challenge is getting the most out of the leading edge FPGA prototyping solutions and that requires a detailed understanding of how this technology works and what FPGA prototyping solutions match your design and verification requirements. That is the whole point of attending #52DAC; finding out what tools and technology works for your design requirements, absolutely.

One of the most recent companies we have been working with is S2C. S2C Inc. is a worldwide leader of FPGA prototyping solutions. They were founded in San Jose, California in 2003 by a group of Silicon Valley veterans with extensive knowledge in ASIC emulation, FPGA prototyping, and SoC validation technologies. The company has been successfully delivering rapid SoC prototyping solutions since its inception. You can see their SemiWiki landing page HERE.

The Vice President of Marketing at S2C is Rob van Blommestein. Paul McLellan and I first worked with Rob at SpringSoft which was later acquired by Synopsys. Next we worked with Rob at Jasper which was acquired by Cadence. Don’t be surprised if Mentor acquires S2C giving Rob the EDA M&A trifecta! You should also check out S2C’s brand new website HERE. This is not S2C’s first DAC but it’s Rob’s first DAC with S2C and let me tell you he can put on a DAC:

Attend Our Seminar:

How to Realize the Genius of Your Design with a Complete Prototyping Platform for Any Design Size, Any Design Stage with Enterprise-Wide Access, Anytime, Anywhere

Register for Demos

Google VP9 and Prodigy ProtoBridge™

  • Link system-level simulation to FPGA prototype
  • Early exploration on FPGA
  • Accelerate verification
  • Increase test coverage

Prodigy Player Pro™

  • Partition design to multiple FPGAs with Pin-Multiplexing Support
  • Configure the prototype
  • Remote system monitoring and control

Prodigy Cloud Cube™

  • Link and manage up to 32 FPGA devices
  • Centralize management of prototyping hardware
  • Multiple Users can share one Cloud Cube simultaneously

Prodigy Neuro™

  • Remotely manage FPGA resources from any location, any time through web-access
  • Manage users, groups and projects
  • Report usages

MIPI with Northwest Logic
Northwest Logic’s Mobile Industry Processor Interface (MIPI) Camera Serial Interface (CSI-2) Controller and Display Serial Interface
(DSI) Controller have been fully validated on S2C’s FPGA Prototyping Platforms.

  • Capture video data through a camera using an CSI-2 interface, storing the data into DDR3 memory, and then transferring the
    data via a DSI channel and display

  • Utilizes Northwest Logic’s MIPI CSI-2 camera controller, DSI display controller and DDR3 controller IP cores
  • Support for multi-lane MIPI CSI-2 and DSI operations and pause capability

Special IP Verification Panel:

IP TRACK: Key Challenges of Verification and Validation of Modern Semiconductor IP

Date:Tuesday, June 9
Time:11:30 AM – 12:30 PM
Location:Room 101

This panel of respected experts will discuss the key challenges of verification and validation of modern semiconductor devices. Topic areas will include verification IP, reusable test benches, best practices for using assertions, hardware prototyping, accelerated models, and emulation. The theme of the panel will be related to how these techniques can be best applied in today’s IP-based design methodologies.

Panelists:

  • Tom Anderson – Breker Verification Systems, Inc., San Jose, CA
  • Toshio Nakama – S2C, Inc., San Jose, CA
  • Bernie Delay – Synopsys, Inc., Hillsboro, OR
  • Raik Brinkmann – OneSpin Solutions GmbH, Munich, Germany
  • Frank Schirrmeister – Cadence Design Systems, Inc., San Jose, CA

Cocktails & Conversation:

Have drinks and appetizers on Rob. Stop by the S2C booth #3108 and you could win a GoPro Hero3!

Monday and Tuesday | June 8 and 9 from 6PM to 7PM

Also Read: Breaking the SoC lab walls

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OneSpin Launchpad, the App Store for Formal Verification

OneSpin Launchpad, the App Store for Formal Verification
by Paul McLellan on 05-21-2015 at 7:00 am
Categories: EDA

Formal verification is qualitatively different from most other verification. A simulation can pass or fail. But while formal verification can prove that the circuit is correct, or incorrect, it can also return “not proven” which means either that the algorithms realized that they were not powerful enough to prove a property, or (more often) that the run time got excessive and it gave up. But there are a number of different approaches to formal verification, and it is only necessary for one of the proof approaches to succeed for the property to be proven (or disproven). It doesn’t matter how many algorithms fail to complete so long as one does. As a result of this multiplicity of approaches, formal verification has increasingly been structured in the form of a base application with apps for different proof methods or different proof applications.

The idea of the app as a small code object that runs in a rich environment was pioneered originally by Java apps running browsers, but it was apps on the iPhone (then copied by Android) that really raised their visibility. However, the thing that made apps really take off was when 3rd parties were allowed to create their own apps, and app-stores made distribution of them straightforward.

In formal verification, traditionally the apps have all been developed by the formal verification companies themselves. Today that starts to change. OneSpin announced this morning their 360-DV Launchpad adaptive formal platform. This is a way to allow 3rd parties to develop apps on top of an encapsulation of OneSpin’s formal technology. There are a number of different business models that are possible, depending on what the 3rd party wants:

  • OEM: app developer OEM’s OneSpin’s technology “under the hood” and has their own branding, channel etc
  • OneSpin App Portfolio: the 3rd party app operates on top of OneSpin-DV verify product, is added to the app portfolio and sold as a reference sell analagous to the app store
  • SaaS: OneSpin’s cloud solution can be leveraged for an instant transaction

The app is not locked in to OneSpin’s technology through proprietary APIs. It uses the SystemVerilog encryption standard, and the launchpad internals give a lot of flexibility. Standard FlexLM licensing is used.

So who are some of the people making use of Launchpad?

  • Tortuga Logic’s Prospect is automated security solution. They OEM launchpad as part of their solution and prospectively look for security issues in hardware such as insecure access to protected regions, encryption keys being exported, and so on
  • Agnisys ARV Formal Register Verification: this takes an English description and formally proves correct operation of the register map and its operation

The big three EDA companies have all acquired and/or developed formal solutions and OneSpin is the only other company focused on formal solutions. Even so a bit of background is probably in order, especially as it is easy to forget that there is a whole EDA world out there beyond the hills around silicon valley.

OneSpin was founded in 2005 as a spin-out of Infineon’s formal verification group. As you might guess with that history it is based in Germany. It has over 30 customers around the world, including many of the top tier electronic companies, and has around 30 employees. Their product line includes automated design analysis, advanced coverage-driven assertion-based verification, and FPGA equivalency checking.

Augmenting traditional simulation-based solutions with formal-based applications has been proven to accelerate the verification process, improve the probability of finding issues, and in some cases provide brand new solutions to difficult challenges. This has lead to a 40% CAGR in the $170M (EDAC 2014) formal verification market.

So the basic idea of Launchpad is that all the expertise and ideas for formal approaches are not inside any one company such as OneSpin (or any of the other guys for that matter). Formal apps can go further if the development is opened up to expert developers.

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Global Electronics Trending Upward

Global Electronics Trending Upward
by Bill Jewell on 05-21-2015 at 12:00 am
Categories: Semiconductor Intelligence, Semiconductor Services

Global electronics production is on a generally positive trend. The chart below shows three-month-average change versus a year ago (3/12 change) for electronics production by country or region in local currency. Total industrial production is shown for Europe and South Korea since electronics production data is not available.

China electronics production growth has remained strong, with April 2015 3/12 change up 11.4% from a year ago. China growth has been 10% or higher since December 2009. Taiwan electronics production has been volatile over the last few years, with 3/12 change ranging from increases over 40% in late 2010/early 2011 to declines approaching 30% in late 2012. Taiwan 3/12 change has been positive for the last eight months, with March 2015 up 7.3%.

Japan electronics production has been on a downward trend for about 14 years as production has shifted to China and other countries in Southeast Asia. Current production (in Japanese yen) is only about one third of year 2000 levels. However Japan is currently undergoing a short term recovery, with March 2015 three-month-average production of 449 billion yen up 44% from the recent low in June 2014. March 3/12 change was 1.7% compared to a 17% decline in November 2014.

Electronics production in the United States and industrial production in Europe and South Korea have demonstrated steady but slow growth. 3/12 change turned positive in Europe in October 2013, in South Korea in December 2013, and in the U.S. in January 2014. The March 2015 3/12 change was about 1% for each region.

We at Semiconductor Intelligence (SC-IQ) have developed a Global Electronics Index based on data from individual countries and regions. The chart below shows three-month-average change versus a year ago for the Global Electronics Index compared to global semiconductor shipment data from World Semiconductor Trade Statistics (WSTS). In 2011 both electronics and semiconductor growth were decelerating following the strong growth of 2010. Semiconductors decelerated more quickly and went more negative than electronics. Semiconductors and electronics both turned positive in mid-2013. Semiconductor growth in 2014 (averaging 10%) outran electronics growth (averaging 5%). In February and March 2015 3/12 change for both semiconductors and electronics were in the range of 5% to 6%.

Semiconductor Intelligence projects the Global Electronics Index will continue to show moderate acceleration for at least the next several months, with year 2015 growth of about 6% to 7%. In the long term, semiconductor growth is a few points higher than electronics growth due to increasing semiconductor content in electronics. Our March 2015 forecast was 8% growth for the global semiconductor market in 2015. The current electronics production data still supports this forecast.

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NFV opens gate for ARM server stampede

NFV opens gate for ARM server stampede
by Don Dingee on 05-20-2015 at 5:00 pm
Categories: Arm, IoT, IP

A couple of years ago, our own Paul McLellan gave us a report on the 2013 Linley Microprocessor Conference with a provocative headline: “Server Shift to ARM Becomes a Stampede”, a title right off one of the Linley slides. 64-bit ARMv8 architecture was relatively new to the game, and ARM share in networking platforms was just a sliver compared to PowerPC, X86, and MIPS.

Since that time, Freescale has become the last PowerPC company standing with AppliedMicro bolting for ARM, and LSI Axxia changing hands a couple of times (and now part of Intel). MIPS has held its ground based on a lead in network processors from Broadcom and Cavium et al. Intel is obviously still a power in servers. I dug around and didn’t find Linley’s updated data, but I suspect the ARM “server stampede” is still mostly on the outskirts of town, trampling PowerPC.

What is the holdup? As someone who has worked around the carrier-grade operating system types for 20 years, I can tell you it’s just not as easy as declaring you have a chip ready for networking infrastructure. The software gate has to be opened. At that 2013 conference, there was some violent agreement. The Linley team suggested it was too expensive for vendors or carriers to create and maintain large code bases on more than one architecture. Broadcom said their stack ran on multiple CPU architectures, which is great – if you happen to use a Broadcom chip and their software.

Let’s put aside the gory details of CPU register sets, SIMD instructions, and even endianness. All those can trip up portability in a huge code base. All can be handled if a given SoC vendor has a good relationship with an operating system vendor, and they provide the right tools for application developers. What is still missing is network-level integration and interoperability – telecom and IoT infrastructure environments are almost never greenfields. Fortunately, the drive for a new architecture and open source support for it are underway.

The real shift of importance is NFV, or network functions virtualization. Instead of building dedicated network appliances, such as load balancers, firewalls, and packet shapers, virtual machines take over the functions running on familiar servers with the necessary network interfaces. Virtualized network functions, or VNFs, are chained into services. These are then orchestrated into carrier-grade services, supporting features like network monitoring, availability, security, and billing.

Open source communities have sprung up around different pieces of the network puzzle. The Linux Foundation’s OPNFV project has established an open NFV reference platform with an emphasis on standardizing APIs between the elements. OpenDataPlane is tackling open APIs for the data plane, which harmonizes different network processor and protocol offload strategies, while maintaining concepts like QoS. There are host of other related initiatives, including OpenStack (cloud), OpenDaylight (SDN), and Open vSwitch (virtualized network switching) to name a few.

What constitutes a “server” is changing, and the cloud, mobile, and the IoT are stirring up a new round of infrastructure wars. This time, it isn’t about the data center and enterprise transactional databases and web services – it’s about moving more packets more efficiently.

ARM understands how to get software on their architecture. With Wind River paired with Intel, and MontaVista linked with Cavium, a logical choice for ARM to turn to for carrier-grade expertise is Enea. An ARM-based OPNFV reference platform, running pieces of Enea COSNOS on an AMD “Hierofalcon” Embedded R-Series SoC with eight ARM Cortex-A57 cores, was demonstrated at NFV World earlier this month. The developer release is being folded back into OPNFV, so more ARM developers can get on the trail.

Qualcomm is among the latest to join AMD, AppliedMicro, Cavium, Freescale and others in the ARM networking infrastructure SoC mix. I don’t think we should call this segment “server chips” anymore, because the network processor and data plane are a big part of the territory. This may resemble more of an orderly cattle drive than a stampede, and it may take longer to move through town than initial projections.

With the open source community behind the move to NFV, the likely move for ARM licensees – working with downstream consumers like Cisco, Facebook, and Google – is to customize SoCs for the task. The move to workload-optimized customization is exactly what sank Intel in mobile, and it could do the same in networking infrastructure if Intel doesn’t respond fast enough. (That Intel-Altera story just won’t go away, will it? “They love us, they love us not, they love us, …”)

The next big challenge for ARM will be develop an infrastructure platform channel. There is quite a gap between larger firms like Dell and HP and Oracle, and smaller companies like Advantech, Kontron, and Radisys. Several have ventured in and not been able to stay, partly because they were burned in telecom boom-bust cycles. This is what people mean when they say ARM can’t succeed without a high-volume server presence. However, PowerPC had a pretty good run in that space between, serving networking OEMs. Will ARM be next up?

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How Microtechnology Will Change Just About Everything

How Microtechnology Will Change Just About Everything
by Tom Simon on 05-20-2015 at 1:00 pm
Categories: Coventor, EDA

When I hear the term micro-technology my first thought is of accelerometers and gyroscopes. However as I’ll explain shortly, micro technology is being applied to a lot more than smartphones and quadcopters. The fruits of development in this area will affect industry, medical, energy, transportation and many other sectors. One of the major players in microtechnology is the Shanghai Industrial µTechnology Research Institute (SITRI), founded by the Chinese Academy of Sciences and the Shanghai government to help drive advances in that they call “More than Moore”.

This initiative seeks to extend and expand the rate of development envisioned by Moore’s Law. For more background on More than Moore look at the ITRS white paper. The goal is to combine traditional IC design with novel packaging such as 3DIC, along with MEMS and other microtechnology. This will catalyze dramatic changes in the nature of products that can be designed and problems that can be solved.

SITRI has been actively building its partnerships. They have an affiliation with the Berkeley Sensor and Actuator Center (BSAC). BSAC’s list of current and past research projects is impressive. One such project is a soot sensor that uses a conductrometric element that changes conductance when soot accumulates. It needs to be cleaned to get new readings. By using MEMS for the sensor, much lower power consumption is achieved during operation and the thermal regeneration process that burns soot off the sensor for new readings.

Another BSAC project proposes using a MEMS device to protect drugs ingested orally from digestive destruction. A so called MucuJet will eject the drugs into the lining of the small intestine using high velocity.The complete list is fascinating. MEMS and micro technology are being used to solve problems in surprising and diverse areas.

Another recently announced SITRI partnership is with Coventor. This partnership makes sense because Coventor specializes in both semiconductor fabrication modeling with their SEMulator 3D, and MEMS design and modeling with their MEMS+. Coventor’s CTO David Fried presented in April at a conference in Shanghai sponsored by SITRI. His presentation on Virtual Fabrication can be found here.

SITRI will use Coventor tools along with the other tools in their process design flow to help produce designs in conjunction with the Shanghai Institute of Microsystems and Technology (SMIT). SITRI will manage a 4” MEMS line, an 8” “Moore to Moore” (MtM) R&D and prototyping line along with an 8” production CMOS line. SITRI received its initial impetus from the emergence of IoT, and have been developing a strong technology base supported by leading partners.

We can expect to see unusual applications for MEMS in conjunction with semiconductor technology. For example, looking again at the BSAC project list there are a number of projects that propose to use MEMS for RF applications. Optics, fluidics, energy storage and generation are also topics included in that list. In short it seems that we are looking at a wholesale explosion of applications for microtechnology. Clearly MEMS has come a long way from the first airbag collision sensors and the novelty of making a miniscule motor on a silicon wafer.

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High-Voltage Power Design

High-Voltage Power Design
by admin on 05-20-2015 at 7:00 am
Categories: EDA

Most of what is talked about on SemiWiki is silicon design. After all for regular SoCs it is the only game in town. But for high voltage power applications (think automotive for one big market) there are other more esoteric technologies becoming more attractive.

Silicon has been the material of choice for high-voltage power applications for a long time. Recently silicon-carbide (SiC) and gallium-nitride (GaN) have started to gain attention. Their wide bandgap means that they should have better performance than silicon. But that wide bandgap also leads to some challenges in modeling due to the accuracy required.

The foundation of designing power devices is TCAD. This “virtual manufacturing” is clearly much faster and cheaper than actually running wafers and the accuracy is really only limited by the mesh size used in the TCAD algorithms: a coarse mesh gives answers fast with some inaccuracy, a fine mesh gives very accurate answers at the cost of increased runtime.

TCAD on its own would be of limited interest if it could not be linked to the design world. The engineers who design the process for power applications are not the same engineers as design the devices themselves. What is required is a link from TCAD to SPICE so that circuit performance can be measured without having to process real wafers, which is both expensive and slow.

Once SPICE models exist then design can proceed much like any analog design, with layout being created, parasitics extracted and then simulations run to determine the performance. Lather, rinse and repeat.

Another key step is reliability analysis. The high voltages involved make electromigration and thermal issues in particular more critical.

Silvaco has a complete suite of tools from TCAD, up through modeling, to get to a PDK. Then a complete suite of tools for design and analysis, including the technologies recently acquired through the Invarian merger.

Two webinars (one in Japanese) go into more details of the Silvaco solution for the design, modeling and simulation of power devices.

The first, by Eric Guichard, is titled TCAD to SPICE Simulation of SiC and Si Power Devices:

  • Key challenges of power device TCAD simulation
    • Size of structure, high aspect ratio and devices that are intrinsically 3D
    • Lattice heating and high breakdown voltage
  • Key challenges of SiC TCAD simulation
    • Wide bandgap
    • Anisotropic physical models and SiC specific models
  • TCAD simulation examples
    • When to use 3D over 2D: 2D is much faster simulation time but it is an inherently artificial device, although 2D can often be used as a pseudo-3D simulation before switching to 3D for accuracy
    • GBT, Trench MOS, DMOS, IEMOSFET
  • Full TCAD to SPICE IGBT flow example
    • Process and Device simulations for IV curve generation
    • TCAD-based SPICE parameter extraction using HiSIM-IGBT compact model
    • Correlation between circuit performance and process variation

The second webinar, presented by Yoshihisa Iino of Silvaco Japan presented a webinar on High-voltage Power Device Modeling using HiSIM_HV2 (the name HiSim comes from University of Hiroshima). The webinar is presented in Japanese.

The webinar provides a comprehensive overview of model parameter extraction for high voltage devices, using the industry standard HiSIM_HV2 model. Model parameter effects of HiSIM_HV2 are explained first, followed by a step-by-step description of model parameter extraction using Utmost IV. Finally, depletion mode, which is implemented in the latest version of HiSIM_HV is introduced.

To access a replay of the webinars, go to the Silvaco webinar page here.

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The Future of Chip Design in the Internet Age

The Future of Chip Design in the Internet Age
by Mike Gianfagna on 05-20-2015 at 1:00 am
Categories: EDA, eSilicon

Huge designs, spectacular design costs, astronomical capital expenditure. Welcome to the present day semiconductor industry. As discussed in my prior post, the days of democratized silicon access have been replaced by an elite market. Custom chips are once again a rich person’s game. Does it have to stay this way? I personally believe everything in the universe is cyclical, so a new era of democratized silicon access is coming.

But what will trigger it? There’s been plenty written about the internet of this or that. OK, the internet of everything. Will this movement be the trigger? I don’t think so. IoT, or IoE if you like will ultimately create demand for custom silicon. That demand will require a *very* efficient, low-risk, cost-managed approach to fulfill it. Something quite different from the highly complex, interdependent processes that were created in the computer age.

We think about evolving business models a lot at eSilicon. A few months ago we conducted some market research on semiconductor customer sentiments around the cloud, big data and internet connectivity. Can these technologies tame chip design problems? The results were enlightening.


Big data analytics was seen by the group as very promising. Respondents identified the massive volume of information that needs to be understood to reduce the risk associated with system-on-chip (SoC) design. Data that comes from all over the world and is constantly changing. The reason this item didn’t make it to “excellent” had to do with a general lack of understanding of what exactly big data is. The gut feeling was that this methodology was the only way to deal with such huge volumes of information, but few could articulate exactly how it would work.

One person in particular conveyed a good perspective on the topic:

“The era of big data is upon us. We will look at 4 elements involved in creating value from big data: 1) collecting distributed data, 2) extracting patterns from noisy data, 3) insights in real-time from flowing data, 4) architecture for chips of the future.”

Use of the internet to flatten the world and efficiently transmit information was a homerun. Virtually all respondents saw the benefits of a semiconductor industry that was online and available 24/7. Using the cloud, well that one was a bit controversial. One person seemed enlightened:

“By utilizing the cloud, design teams can have input and real-time data from home, office or anywhere a secure connection can be obtained.”

A lot of folks worried about security. After reading a lot of responses, I can paraphrase as follows:

“I’ll put my life savings and maybe my most sensitive photos in the cloud, but my design’s RTL – NO WAY!”


I think this will change over time. We’ll see. All this research told us the customer base believes that big data and the internet hold promise for the future of chip design. We have believed that for a long time, so the customer validation was good. Leveraging these technologies can create a more transparent semiconductor design and procurement environment – one that supports self-service automation and real-time feedback. A more democratized market – again. There are many, many opportunities to improve the customer experience as the semiconductor industry goes online, so there will plenty to discuss.

We recently announced a second-generation internet-based platform for IP evaluation and IC design optimization, quoting and work-in-process tracking. It’s an ambitious project to put the semiconductor business online. Take a look at what we’re up to. I’d like to hear your comments.

From Mike Gianfagna of eSilicon


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A Key Partner in the Semiconductor Ecosystem

A Key Partner in the Semiconductor Ecosystem
by Pawan Fangaria on 05-19-2015 at 5:00 pm
Categories: Ansys, Inc., EDA

Often we hear about isolated instances of excellence from various companies in the semiconductor industry which contribute significantly in building the overall ecosystem. While the individual excellence is essential, it’s rather more important how that excellence is utilized in a larger way by the industry to create a ‘value greater than the sum’.

This is evident from ANSYS’ insightful presentations on their tools and technologies and their participation with several customers and partners in the upcoming 52[SUP]nd[/SUP] DAC. We know about the key features of ANSYS simulation tools, such as accuracy, versatility, comprehensiveness including chip, package and system, capacity, performance, and so on that drive the design towards higher reliability and quality with faster design closure. Also, ANSYS tools’ qualification with Intel’s14nm Tri-gate and TSMC’s 10nm FinFET and 16nm FF+ technology nodes makes them capable of solving design problems at leading edge technologies. This week when I reviewed ANSYS’ DAC agenda, I realized that ANSYS simulation technologies have become key enablers in the overall ecosystem of SoC designs. The participation of customers and partners including industry segment leaders, IP providers, foundries and design houses into ANSYS activities showcasing their simulation technologies is witness to the growing importance of ANSYS technologies in the semiconductor ecosystem.

In today’s SoC ecosystem where designs are exceeding a billion gates including several IP blocks for different functions, and chips being manufactured at extremely thin metals and narrow noise margins, multi-physics simulations at various levels of abstractions are essential. The simulation results need to be highly accurate at individual IP level as well as the complete SoC level. Various simulation engines are required to estimate and analyze different parameters of a design such as power, IR drop, temperature, electromigration, EMI, ESD, and so on. ANSYS has put together a set of presentations and demonstrations involving multiple tools to provide solutions to control these parameters in order to optimize the designs for best power, performance, cost and reliability. These will be presented by subject matter experts at ANSYS and co-presented along with their partners in a few cases.

ANSYS’ presentations reflecting best practices in design development and verification include –

  • Driving low-power design with physical-aware RTL power budgeting methodology
  • Achieving faster power design closure with integrated chip-package co-analysis
  • Design-aware power grid prototyping
  • Enabling silicon success of power-efficient andreliable FinFET IP designs
  • Best practices for ensuring ESD integrity at IP and SOC using PathFinder
  • Achieving thermal-aware EM through chip-package-systempower-thermal convergence in 3DIC designs
  • Ensuring chip-aware system-level power and signal integrity analysis
  • Rethinking the Power Analysis Flow

There are interesting customer workshops (by invitation) presented by leading semiconductor companies such as Samsung, Avago, Infineon, Freescale and others –

Monday, June 8: Methodologies for Ensuring Timing, Reliability and Thermal Integrity

This will include the following topics:

  • Clock Jitter Analysis Flow using RedHawk-PJX
  • Achieving Power and Reliability Sign-off for Automotive SemiconductorDesign
  • Thermal Integrity and Thermal-aware EM Reliability Check for 3DStacked Dies in Automotive Application
  • IntegratingPathFinder into a SoC ESD CAD Sign-off flow


Tue, June 9: Accelerating IC / System Design Closure for Power and Reliability

This will include the following topics:

  • Automated flow fortechnology/design specific power grid design
  • IR Analysis of Large ICs through DistributedMulti-processing (DMP) Technology
  • Accurate SiliconCorrelation using Chip-Package Co-analysis
  • Power Integrity Analysis ofa Combined PCB, Package and Die


Wed, June 10: Designing for Low-Power and High-Performance SoC

This will include the following topics:

  • Early Power Grid Prototyping Flow
  • Distributeand Conquer – Taming Power-integrity Sign-off Challenges of Gigascale Designs
  • Reference Flow and RTL Power Methodology for Energy-Efficient IP and SoCDesigns for Mobile Applications
  • Accurate and Early Power Prediction Enables Better Power Efficiency and Faster Design Closure


Then there will be several entertainment items and industry level presentations in the open theatre at ANSYS booth #1232. Also there will be presentations focused on leading foundries and different industry segments such as IoT, automotive, and mobile at collaborated booths:

Automotive Village, booth #1303
ARM Connected Community, booth #2414
TSMC OIP, booth #1933
Samsung Electronics, booth #933.

Check the detailed abstracts of various presentations at the ANSYS website here. Click the “presentation & demo schedule” to review abstracts and choose the best sessions according to your preferred time. Click the “registration” link to register for the sessions.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

Posted on

Custom IC Panel: Winning the Custom IC Design Race!

Custom IC Panel: Winning the Custom IC Design Race!
by Daniel Nenni on 05-19-2015 at 12:00 pm
Categories: EDA, Solido

Back in the day, EDA companies enabled the foundries. Seriously, those pesky little foundries chased us EDA companies around like puppies who needed a walk. Now, emerging EDA and IP companies are the puppies and we chase the foundries. Solido Design Automation is one of the hardest working puppies that I have ever helped with strategic foundry relationships. I know them well and can tell you that Solido is THE most exciting EDA company focused on custom IC design today. They are technology and market leaders with 90% revenue growth last year, absolutely.

Solido will be a busy little pup at #52DAC next month. They will be hosting a Custom IC Panel

Winning the Custom IC Design Race at Nanometer & Low Power Processes

which will discuss how companies are navigating the tradeoff between reducing underdesign to improve yield, and reducing overdesign to improve power, performance and area. Panelists will share techniques to accelerate high performance, low power custom IC design, while reducing risk of re-spins due to increased variation at nanometer and low power process nodes. Memory, standard cell, custom digital and analog/RF design applications will be discussed.

Panelists include Alfred Yeung (Applied Micro Circuits), Dragomir Nikolic (Cypress Semiconductor), Sifuei Ku (Microsemi) and Jeff Dyck (Solido). Solido CEO Amit Gupta will be giving an opening presentation on custom IC market data. Register here for the panel: https://www.surveymonkey.com/s/7CPXFM6

This is my all time favorite Solido slide. See the guy falling off the edge? That’s you if you don’t use Solido Variation Designer. Especially if you are designing with FinFETs!

Solido will be presenting at the TSMC DAC OIP Theater on their software integration at TSMC FinFET and low power processes. Dates and times will be announced shortly.

Solido will also have 3 demos at the DAC booth, showing how their product is being used in industry for memory, standard cell, and analog/RF/custom digital design. Details are below, register here for a demo: http://www.solidodesign.com/page/dac-2015-demo-signup/

Solido Variation Designer for Memory
Full Chip Memory and Cell Level Statistical Verification
See how Solido’s customers are using Variation Designer for memory design:

  • Hierarchical Monte Carlo: Verify full-chip memories with perfect statistical accuracy with Solido’s newest memory technology

    • Statistically correct verification of replicated structures
    • Correct application of both global and local variation
  • High-Sigma Monte Carlo: Verify columns, bitcells, sense amps, and other memory blocks to high-sigma quickly and with perfect Monte Carlo and SPICE accuracy
  • Scale to support real-world circuits (such as memory columns and critical paths)
  • Solve pass/fail, binary, and multi-modal output measurements
  • Efficiently debug high-sigma variation problems
  • Produce trustworthy high-sigma verification results
  • Variation Designer 4.0: Preview Solido’s upcoming Variation Designer major release with a suite of brand new features for memory designers

Solido Variation Designer for Standard Cell
Statistical Verification and Sizing of Cell Libraries
See how Solido’s customers are using Variation Designer for standard cell design:

  • High-Sigma Monte Carlo: Fast, accurate, scalable, and verifiable high-sigma verification of standard cell libraries

    • Accurately capture performance and power vs. sigma tradeoffs for the entire sigma range
  • Cell Optimizer: Fast, accurate optimization of standard cells
  • Variation-aware optimization across PVT corners, Monte Carlo corners, and High-Sigma Monte Carlo corners
  • Highly flexible setup of variables, goals, and constraints
  • Batch operation for optimizing complete cell libraries
  • Variation Designer 4.0: Preview Solido’s upcoming Variation Designer major release and its suite of enhancements for batch analysis of standard cell libraries

Solido Variation Designer for Analog/RF and Custom Digital
Statistical & PVT Verification and Debug
See how Solido’s customers are using Variation Designer for analog/RF and custom digital design:

  • Statistical PVT: Solido’s all-new capability delivers unprecedented accuracy and coverage across 3-sigma statistical variation and operating conditions
  • Fast PVT: 2-50X faster verification across corners & operating conditions
  • Fast Monte Carlo: Fast, accurate 3-sigma verification & corner extraction
  • High-Sigma Monte Carlo: Fast, accurate, scalable, and verifiable high-sigma Monte Carlo verification and design for analog/RF and custom digital circuits
  • Variation Designer 4.0: Preview Solido’s upcoming Variation Designer major release and its enhancements to make variation-aware design of analog/RF and custom digital circuits even faster, more thorough, and easier than ever

Register here for a demo: http://www.solidodesign.com/page/dac-2015-demo-signup/

Bottom line:Solido wrote the book on variation, literally. See a Solido demo at #52DAC and get one while they last!