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Synopsys Earnings Call

Synopsys Earnings Call
by Paul McLellan on 05-27-2015 at 12:00 am
Categories: EDA, Synopsys

Synopsys had their earnings announcement and call last week. They were good. In Aart’s own words:I’m happy to report that our second quarter results were very strong and solidify our outlook for the full year. We delivered revenue of $557 million, non-GAAP earnings per share of $0.68 and $155 million in operation cash flow. We’re raising the midpoint of our revenue guidance, with a range of $2.210 billion to $2.235 billion, and our non-GAAP EPS objective to a range of $2.76 to $2.81, double-digit growth at the midpoint.

Aart reiterated Synopsys’ 3-pronged product strategy:

  • Leadership in EDA for next-generation chips
  • Grow the IP offering
  • Invest in software quality and security solutions

He gave some interesting color on tapeouts:The number of active FinFET designs and tape-outs to-date again grew almost 15% in just the last quarter, to well over 200. Synopsys is relied on for approximately 95% of these, and our momentum continues, as more and more enterprises commit to FinFET and count on us for success.

I think you have to take the “relied on” with a grain of salt since I’m sure many of those tapeouts also “relied on” other vendors since big companies often have all the physical design tools and use whatever seems best for that part of the design.

One thing that may be significant or not is:Our custom design solution is also gaining strength, and in fact we successfully displaced the incumbent at a global medical device company, who is now using a complete Synopsys digital-and-custom flow.

Synopsys has tried for years to build a strong bridgehead in custom design with only limited success and Virtuoso has remained the incumbent almost everywhere.

On to place and route. Here Synopsys claim that ICC2 is faster than any of the competition (including the newly announced stuff):Customers report that IC Compiler II is dramatically faster than any tool on the market today, including next generation offerings touted by competitors.

Who knows what the reality is since those competitors claim speed advantage too. Again, the reality is probably that on some designs ICC2 is a lot faster and on other designs, not so much.

Next up, verification:where approximately 80% of advanced designs rely on the Synopsys solution as their primary simulator.

Again I’m not sure that “rely on” means what it says. I can believe 80% of advanced designs use Synopsys VCS but not that they do so exclusively.

As to IP, Synopsys:are the number one supplier of interface, analog, memory, and physical semiconductor IP

If RAMBUS isn’t counted since it doesn’t seem to be (and it’s business is multi-faceted, not just IP) then ARM is #1 and Synopsys is #2 in the IP market.

In the software quality and security space, built around the core of the Coverity acquisition. This includes the recent Codenomicon acquisition. The group has been renamed and is now called the Software Integrity Group.A year after acquiring and integrating Coverity, we’ve learned the following: Coverity was a great acquisition, a compelling combination of the familiar and the new, and a platform we can build on. Specifically, we acquired excellent technology, the expanded customer base, and a brand new TAM.In order to scale the operations to a grander level, it’ll take ongoing investments in sales and marketing, as well as in R&D…We expect the Software Integrity Group to be slightly dilutive in the second half of the year.

What they are saying is that they are going to invest more in the space at the expense of profitability. This got asked about in the Q&A.when we originally acquired it, in our initial plan, we expect it to be breakeven in the second half of the year that – now, that we know much more and now that we’ve also decided to make some additional investments specifically in broadening the language coverage that is why we specifically communicated at the end of the second half it would be slightly dilutive. But it’s very small

Another thing asked in the Q&A was about the lawsuit with Mentor. Aart said that he could not say much but what he did say was:I will minimize my comments on this, after the verdict of course there was a set of issues we have to deal with, the version that’s on the market today does not violate any of that. And so, we see that our business is doing well.

I’m not sure what that means about the installed base of Zebu boxes that the court found did infringe. But at least going forward things seem to be clean. Aart was asked how fast emulation was growing but he wasn’t biting on that bait:we said that it’s doing very well. We don’t disclose the growth rates of individual product. They tend to go up and down, but I would reiterate that we think that we have a very strong emulation solution.

So all in all, a great quarter for Synopsys. No big surprises on the call that I noticed. A little bit of additional color on Synopsys’ overall business.

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Why does Apple do business with Samsung?

Why does Apple do business with Samsung?
by Daniel Nenni on 05-26-2015 at 10:00 pm
Categories: Foundries, Intel Foundry, Mobile, Samsung Foundry, TSMC

The Apple and Samsung relationship is an interesting one. On one hand they have co-developed some of the most innovative products on the market today (iPod, iPhone, iPad, iWatch) yet they are fierce competitors in the mobile market. Some call this type of business relationship “frenemies” others refer to the old Italian proverb “keep your friends close, but your enemies closer.” Personally I refer to it as “foundry business as usual.” Let’s take another look at the Apple/Samsung relationship and see if we can get a better picture of what is really going on here. This of course is based on my experience, observations, and opinions so feel free to correct me if I’m wrong, but I’m not.

Apple became a chip company in the early 1990s with the assistance of VLSI Technology. This was using the ASIC business model where Apple could “toss” an RTL level design over to VLSI and have them deliver finished chips. The first chip was for Apple’s PDA, the Newton, which lost out to the much easier to use BlackBerry and Palm Pilot.

The smartphone (iPhone) was the next device to usher in semiconductor design at Apple. In 2007 the first iPhone was powered by the APL0098 SoC designed by Apple and the newly created Samsung Foundry Division using the same ASIC business model that VLSI Technology pioneered. The first chip used Samsung’s 90nm technology which was one process behind TSMC’s 65nm that offered twice the gate density and a power reduction of up to 50 percent.

The next two iterations of the Apple SoC were released in 2008 and 2009 using Samsung’s 65nm technology. At the same time TSMC was delivering 40nm chips with twice the density of 65nm with significantly reduced power requirements. In 2009, 2010, and 2011 Apple used Samsung’s 45nm which delivered density and power requirements just below TSMC’s 40nm. In 2012 and 2013 Apple used Samsung’s 32nm process but TSMC was already at 28nm which again offered increased density and lower power. At the end of 2013 (iPhone 5+ and iPad Air) Apple used Samsung’s 28nm. Apple also ushered in the 64-bit smartphone with the iPhone 5s beating industry SoC leader Qualcomm.

For the iPhone6 and iPad Air2 in 2014, Apple switched to TSMC’s 20nm which offered a 1.9x density and 25% power advantage over 28nm. The switch from Samsung Foundry to TSMC is a hotly debated topic especially since Apple is now back at Samsung for the 14nm A9 to be released in September of 2015. According to analyst estimates, Apple paid Samsung $2.7 billion for chips in 2014 which is significantly lower than the $4.3 billion Apple paid Samsung in 2013. So yes, the Apple business is a very big deal for the foundries, absolutely.

Apple claimed its semiconductor manufacturing independence with the 2008 acquisition of P.A. Semiconductor and the 2010 acquisition of Intrinsity which enabled them to move from the ASIC business model to the fabless semiconductor powerhouse they are today. If you want my opinion, which clearly you do if you are reading this, Apple bases the process technology decisions on technology and the ability to deliver said technology, simple as that.

I know that Apple evaluated TSMC’s 28nm for the A6 and A6x SoCs but since TSMC was the only foundry yielding at the time TSMC’s 28nm pricing and capacity were in question. At 20nm however, Apple wrote TSMC a very large check to get right-of-first-refusal and most-favored-nation pricing which squeezed out competing SoC vendors (QCOM, MEDIATEK).

At 14nm Samsung developed an LP process specifically for Apple which started risk production in Q4 of 2014 making it viable for the Apple A9 SoC (iPhone 6+) release in Q3 2015. The big shocker here is that Samsung released their own 14nm SoC (Exynos) for their flagship mobile device the Galaxy S6 in the first half of 2015 beating everyone’s 14nm delivery expectations, including my own.

TSMC was two quarters behind Samsung with their higher performance 16nm FinFET++ implementation which will be used in the lower volume Apple A9x SoC business for the iPad refresh in Q4 2015 (the A9 versus A9x volumes are reportedly 70% versus 30%). I also heard that Apple evaluated Intel Custom Foundry 14nm, but to no avail.

10nm will be the next foundry battleground. Samsung and TSMC have both discussed taping out 10nm customer designs in the fourth quarter of 2015 which fits the timeline for Apple’s next product refresh using the A10 and A10x SoCs. Intel on the other hand has been very quiet which is not necessarily a good sign for the competition. Intel surprised the industry with 22nm FinFETs. Another 10nm surprise could certainly be in the making. My guess is that Apple will go to TSMC for 10nm but at this point it is just a guess.

Bottom line: Today, Apple is clearly the most influential foundry customer worth billions of dollars in revenue annually. Apple’s regular product refresh is now driving the foundries harder than I have ever seen and that includes Intel and Samsung. Competition is what makes the fabless semiconductor ecosystem strong and who better than Apple to lead that effort?

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Taking a Leap Forward to Prototype Billion Gate Designs

Taking a Leap Forward to Prototype Billion Gate Designs
by Pawan Fangaria on 05-26-2015 at 12:00 pm
Categories: EDA, FPGA, S2C EDA

It’s very common these days to hear about a billion gates SoC, but not without a huge design and verification effort and investment of resources. A complete verification of such an SoC needs several verification steps including software and hardware based methodologies that often are not sufficient to cover the whole SoC. In order to complete test coverage for the SoC, it is gradually built while employing different methods of verification. Clearly, the verification is tedious, time consuming, resource intensive and without full confidence. What if we have a complete prototyping system that has hardware as well as software that can partition the design, link with system-level simulation environment, and provide control, monitoring and debug facilities?

In the recent past FPGA-based prototyping solutions have tried to ease the design and verification process in a cost-effective manner, but they lacked in several aspects including completeness, generality, capacity, scalability and availability. Recently a promising solution, ‘Prodigy[SUP]TM[/SUP] Complete Prototyping Platform’ was announced by S2C.This is a FPGA-based complete prototyping platform for an SoC design at any stage, for any design size, and accessed from multiple locations across the world. The realization of this platform has been further strengthened with the introduction of ‘Prodigy[SUP]TM[/SUP] Cloud Cube[SUP]TM[/SUP]’, an enterprise-class, FPGA-based prototyping system.

The Cloud Cube 32 has a large capacity that can hold up to 32 FPGAs in a single chassis. The Cloud Cube can accommodate FPGAs from different vendors. With 32 Virtex-7 2000Ts, the total capacity can go up to 640 million ASIC gates. And the capacity with 32 Virtex-UltraScale 440s from Xilinxcan go up to 1.4 billion ASIC gates. The FPGAs can be installed using different combinations of S2C’s Quad, Dual, or Single Prodigy Logic Modules and flexible interconnection modules or cables.

The prototyping platform is versatile enough to accommodate the designs at any stage and with any size. And this can be accessed by designers sitting at multiple locations across the world, thus making the platform available to designers outside the traditional closed door hardware prototyping or test lab. A group of 16 designers can simultaneously use different Prodigy Logic Modules in a Cloud Cube. Each Logic Module is remotely accessible through Ethernet. There are 16 independent PCIe fast data ports for data transfer between host and Cloud Cube. Different designs or multiple instances of the same design can run concurrently in a Cloud Cube.

There is superb controlling and monitoring mechanism provided in the system. The Prodigy Logic Modules can be automatically recognized and the interconnection between them automatically detected. The IP address, power, I/O voltages, currents and temperatures of the Logic Modules can be monitored round the clock. There can be 6 global clock sources to all Logic Modules with less than 200ps skew. There are 6 programmable clock sources (0.2 ~ 700MHz) and 3 internally generated clocks from any FPGA for clocking the design. Also, there are 3 global resets provided to all Logic Modules which can be triggered through push button or remotely through software. The system is equipped with self-tests that can quickly isolate design issues from hardware or connection issues.

The mechanical design of the Cloud Cube is ideal from all perspectives such as flexible cable connections, easy to handle in accessing or mounting Logic Modules and daughter cards (S2C provides a library of more than 80 Prodigy Prototype Ready daughter cards), maximum cooling, and so on.

For completeness of the prototyping environment, the Cloud Cube is supported by state-of-the-art tools such as Prodigy Player Pro for importing designs, partitioning them, and running P&R; Prodigy Debug Module (coming soon) for concurrently debugging multiple FPGAs in a single logic analyzer in the Cloud Cube; Prodigy ProtoBridge which links the system-level simulation environment to the FPGA-based prototyping platform; and Prodigy Neuro (coming soon) to manage multiple Cloud Cubes and/or Logic Modules that are used by global design teams through the web.

The SoC prototyping through Cloud Cube is a breakthrough approach that provides unprecedented capacity and scalability for billion gates designs managed over a private cloud and worked upon by design teams spread across the world.

This appears to be one of the major innovations being unveiled in the 52[SUP]nd[/SUP] DAC. S2C will showcase Prodigy Cloud Cube working with their complete FPGA prototyping solution at their booth #3108. Don’t forget to visit the booth.

More information from S2C about their Prodigy Cloud Cube HERE.

Also read the following to know more about S2C’s FPGA prototyping solution:
A Brief History of S2C: A Vision for FPGA Prototyping Realized
S2C eyeing 1B gate FPGA-based prototypes

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

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How Good Is Your Library? Are You Sure?

How Good Is Your Library? Are You Sure?
by Paul McLellan on 05-26-2015 at 7:00 am
Categories: EDA

 

One task that is not very exciting but is critical is that of library quality assurance. Many design groups have created their own procedures, often having been burned in the past, to ensure that the libraries that they use are good. Failure to do so has resulted in:
Continue reading “How Good Is Your Library? Are You Sure?”

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How to design silicon photonics–take this class!

How to design silicon photonics–take this class!
by Beth Martin on 05-25-2015 at 9:30 pm
Categories: EDA, Siemens EDA, Silicon Photonics

Silicon Photonics is the hottest prospect for blazing fast communication between chips in servers, data centers, and supercomputers.

By using light instead of electrical signals, it promise to usher in a new standard of high performance, low power devices while extending the use of more mature process nodes, helping to reduce overall costs. Of course, nothing comes completely free. While it may be possible to utilize the same fabs and manufacturing techniques, as demonstrated recently by IBM (SPIE 2015), the design and testing of photonic devices is quite different than that of the traditional IC. Learning how to design silicon photonic circuits takes some effort, and doing it on your own is a tough task.


Fortunately, there is now an online course, which starts on 7 July, 2015,available through edX that can give you hands-on practice in the design of photonic circuits. Under the instruction of Professor Lukas Chrostowski, a leader in the field, you will actually step through the entire process of design creation, simulation, and verification of a silicon photonic circuit. For this course, Mentor Graphics is providing students with access to the Pyxis IC layout tool and the Calibre physical verification tools required to create and verify photonic circuit designs using a secure remote cloud infrastructure.

This 6-week course allows you to create, edit, and upload real design data. The upload calls Mentor Graphics’ Calibre tools to perform error checking (for compliance to manufacturing constraints and design testability requirements), and performs mask aggregation and generation of automated test vectors. It also enables students to perform peer design reviews and provide feedback on each other’s designs.

When completed, the student designs will be collected and actually manufactured! The manufactured circuits will then be tested using a novel photonic test bench approach. While you won’t have access to the final manufactured chip, you will receive the results of the post-manufacture test results for analysis and validation of their design approach.

Ultimately, this training could help you dramatically cut your learning curve and shorten the leap to the rewards of silicon photonics design. Interested? Get more information and register for the course here.

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CEVA DSPs and the Tale of Two Chip Underdogs from China

CEVA DSPs and the Tale of Two Chip Underdogs from China
by Majeed Ahmad on 05-25-2015 at 1:30 pm
Categories: Ceva, EDA, Mobile

Leadcore Technology Co. Ltd, a subsidiary of Datang Group, is a silicon success story from China. It recently made waves by snatching the baseband socket from Qualcomm in Xiaomi’s sub-$100 LTE smartphone Redmi 2A. Leadcore’s L1860C chipset included quad-core 1.5GHz CPU and Mali-T628MP2 GPU from ARM and LTE modem from CEVA Inc.

What happened next? Xiaomi snatched Leadcore as a silicon partner to go vertical like smartphone rivals Apple, Huawei and Samsung. Marshal Cheng, a senior executive at Leadcore, recently spoke to EE Times to share the details of how the fabless chipmaker will collaborate with Xiaomi in developing customized processors.

Cheng also talked about the fabless firm’s early struggles while dealing with IP products like ARM and ZSP cores. According to Cheng, Leadcore’s real breakthrough came in 2012, when it teamed up with CEVA and licensed its software-defined radio (SDR)-based modem solution. That laid the foundation of Leadcore’s ambitious roadmap for LTE chips and also won Xiaomi’s attention.

It’s worthwhile to note that modems, especially multimode LTE modems are hard to design. A baseband processor digitizes and compresses the voice signal, modulates it onto a wireless signal, and carries it through the wireless infrastructure and vice versa. It’s highly challenging for chip designers to create a powerful communication processor that meets stringent power constraints.


Software modem replaces dedicated baseband system

The CEVA-XC, a fully programmable solution, supports multiple air interfaces in software, including LTE, HSPA+, 3G, and 2G. The flexibility of a software modem allows system-on-chip (SoC) designers to handle previously separate functions on a single DSP and gain a significant reduction in cost and power. In other words, instead of building separate chips for each wireless standard, baseband designers can build a single chip that can adapt to each market with a simple change of software.

Will Strauss, President & Principal Analyst at Forward Concepts, acknowledges CEVA’s role in redefining the DSP architecture. “CEVA introduced special-purpose DSPs such as the CEVA-XC that enable software-based modems and a unified platform for Wi-Fi, 3G, LTE and LTE-A with power and die size on a par with fixed-function modem designs.” CEVA’s configurable processor cores can also scale across a wide range of performance levels and enable the high reusability and fast time-to-market.

Leadcore, like most of the SoC houses in China, uses microprocessor cores from ARM. Strauss notes that another crucial factor in CEVA’s success is its close collaboration with ARM. CEVA ensures comprehensive support for the latest industry-standard interconnect and coherency protocols, enabling their mutual customers to leverage the inherent advantages of designing ARM plus CEVA-XC multicore SoCs.

Spreadtrum: China’s Baseband Pioneer

In retrospect, Leadcore’s decision to use CEVA’s soft modems was spot-on. The modems for LTE-based 4G wireless devices require almost twenty-fold increase in processing horsepower compared to 3G modems. So replacing dedicated baseband systems with the software approach came as a welcome relief to mobile SoC makers like Leadcore.

The second tale of CEVA’s association is about another ARM licensee in China: Spreadtrum Communications. However, unlike Leadecore, the relationship of CEVA and Spreadtrum goes back to the early 2000s, when mobile phone makers mostly employed specialized baseband ASICs. Spreadtrum, soon after its inception in 2001, joined hands with CEVA and the outcome of their partnership was SC6600, the first baseband chip for GSM/GPRS handsets developed in China.

Then, in November 2004, Spreadtrum announced that it has successfully developed the multi-band chipset SC8800, the first complete mobile SoC supporting GSM, GRPS and TD-SCDMA standards. Spreadtrum was the first company in China to develop baseband solutions for the country’s homegrown TD-SCDMA 3G standard. Time Division Synchronous Code Division Multiple Access or TD-SCDMA is air interface for China’s 3G wireless standard. The world’s first baseband chipset for the China 3G standard—powered by CEVA’s low-power Teak DSP core—was developed in less than one and half years.


Spreadtrum’s Mocor platform is customizable turnkey solution for handset OEMs

Later, in 2006, Spreadtrum expanded its design partnership with CEVA when it licensed the CEVA-X1620 DSP and CEVA-XS1200 sub-system for its upcoming 3G wireless baseband processors. Spreadtrum made a strong bet on TD-SCDMA standard at a time when industry watchers were skeptical about its potential amid the intense two-way race between the European W-CDMA and Qualcomm-backed cdma2000 standards.

Spreadtrum’s gamble on this brand new 3G technology paid handsomely and now it leads China’s TD-SCDMA smartphone market with more than 50 percent of market share. In April, the second largest chipmaker in China made the long-awaited leap of faith toward LTE-based 4G wireless and announced volume shipments of its quad-core 5-mode LTE platform, SC9830A. Again, the SC9830A chipset is based on DSP cores licensed from CEVA.

It’s worthwhile to note that CEVA has been among the semiconductor outfits that focused on China early on. According to the quarterly results, CEVA completed 12 new license agreements during the first quarter of 2015, and six of the new licensees are based in Asia. In other words, nearly half of company’s DSP core and connectivity IP business comes from Asia.

Also read:

CEVA DSP Cores … Inside Intel

CEVA Eyes DSP Scale in China’s $65 LTE Handsets

CEVA and LTE: Happy Together

Majeed Ahmad is author of books Age of Mobile Data: The Wireless Journey To All Data 4G Networks and Essential 4G Guide: Learn 4G Wireless In One Day.

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How Good is Your DRC Deck?

How Good is Your DRC Deck?
by Daniel Nenni on 05-24-2015 at 4:30 pm
Categories: EDA, Sage DA

Design Rule Check (DRC) is the #1 foundry sign-off check. Fabless companies receive the DRC deck from the foundry; it’s a file comprising thousands of commands in a proprietary checker language for a specific DRC tool. In advanced technologies such a deck executes tens of thousands of geometric operations on the physical design data as it tries to detect violations of the foundry design rules.

Design rule compliance is a very big deal. Today’s advanced technologies require single-digit nanometer precision and don’t leave any wiggle room for deviations. A design that goes to tape-out represents a cost of $30M to $100M and an error could cost millions more in new masks and wafers, not to mention the cost of missing the product schedule. We would therefore expect that there is enough design automation in place to ensure that the DRC deck is an accurate derivative of the design rule specification.

The reality in this corner of EDA is quite different though:
[LIST=1]

  • The first astonishing fact is that until recently there has not been an EDA solution for design rule specification. The closest thing to a spec that designers had access to was the design rule manual (DRM) that holds free format description of design rules. These descriptions are informal and sometimes unclear but most importantly, are not machine readable. There is no automated system that can read these descriptions and process them for downstream tools.
  • This brings us to the main problem: lacking such an EDA solution, the DRC deck is programmed manually based on human interpretation of the rule. To validate this complex piece of code we would want the DRC deck to be verified against the rule spec but if there is no spec – how do we know that the deck is correct and represents the true, accurate, and complete intent of the design rule?

    A very good question. Lacking an EDA solution, what usually happens is that the newly developed DRC deck is run on test chips and preliminary design blocks and the results are compared against process simulation or actual silicon to ensure that manufacturing errors are detected by the DRC and that no false errors are flagged. If incompatibilities are found, the DRC deck has to be modified and hopefully the DRM is updated as well. This practice is very cumbersome, expensive, and slow, but the biggest problem is that it relies on these few test chips and blocks that cannot represent all possible errors that can and will be made by designers. This is one of the reasons early DRC decks are changed and updated as more and more designs are being taped out. Eventually, when the DRC deck has “seen” enough designs, and updated accordingly, we consider it mature.

    Getting back to: How Good is Your DRC Deck?

    It’s hard to tell. What we really want is a rule-by-rule validation report produced by a system that runs the DRC deck and validates it against a formal design rule specification.

    Well, Sage-DAaddresses this very problem and offers such a solution. Their iDRM platform enables engineers to capture design rule specifications graphically – quickly creating a clear and formal description. These rule specs are also executables – they can immediately run a check for the captured design rule.

    Sage-DA recently went a step further with their new DRVerify tool that generates a systematic and exhaustive set of test cases from that rule specification. The generated test-suite accurately represents the design rule intent and provides an input test pattern to the DRC deck under development verifying they catch all possible rule violations without false errors.

    Check out #52DAC booth 1924 and have a chat with my good friends at Sage Design Automation!

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    Accelerate Modern PCB Design and Manufacturing

    Accelerate Modern PCB Design and Manufacturing
    by Pawan Fangaria on 05-24-2015 at 12:00 pm
    Categories: Cadence, EDA

    In modern electronic industry PCBs are required to accommodate highly dense circuits with large number of components and complex routing spaces. While the complexity is increasing, the time-to-market is decreasing. In such a scenario, there is no other option than to reduce the design time by employing innovative editing options and make the design correct-by-construction for manufacturing so that the cycles between design and manufacturing are eliminated. Moreover, designs may need customized rules which should be easy to develop and use. Also, frequent changes in fabrication technologies require new rules to be developed in a timely manner. It’s very pleasant to see that with rapid increase in circuit sizes and complexities, PCB tools and technologies have also evolved by a large extent.

    A few days ago Cadencereleased its Allegro 16.6-2015 product portfolio that introduced several new capabilities to address modern day challenges in PCB designs, make designs more predictable, and shorten the overall design time up to manufacturing. It was a nice opportunity talking to Hemant Shah, Product Management Group Director at Cadence who explained in detail about all these new capabilities.

    Allegro provides an integrated environment for electrical, physical and manufacturing verification. In Allegro 16.6, the Allegro Manufacturing Option includes DFM (Design for Manufacturing) Checker, Documentation Editor, and Panel Editor. The DFM Checker provides manufacturing analysis tools for designers to analyze and correct fabrication related issues before sending the design for fabrication, thus eliminating cycles between design and fabrication and making the design more predictable. The Documentation Editor is an intelligent documentation-authoring tool that automates the complete process for fabrication documentation. It creates the complex PCB documentation for handoff to manufacturing in a fraction of time compared to traditional way of documentation. This is streamlines manufacturing handoff eliminating unnecessary scrap and iterations with manufacturing partners. The Panel Editor automates the complex process of assembly panel documentation. It enables designers to quickly create manufacturing documents that clearly articulate the panel specification and instructions for successful fabrication, assembly, and inspection of their designs. Cadence customers have observed this efficient fabrication and assembly document generation process to be faster than traditional methods by 60% or more.

    The Allegro Rules Developer and Checker provides flexibility to extend supported rule sets. It provides a ‘relational geometric verification language’ designed specifically for creating rules that are proprietary and custom to an original equipment manufacturer (OEM). The tool supports constraint driven flow where the rules can be viewed and executed from the Allegro Constraint Manager making it a single source for all DRCs within a PCB. This also enables designers develop new rules according to changing fabrication processes or even new fabrication technologies.

    The Allegro 16.6 provides excellent capabilities for routing and tuning high-speed interfaces such as DDR3, DDR4, PCIe, and so on. These interfaces operate at high bandwidth and low voltage, and are increasingly susceptible to crosstalk. The timing closure is a significant challenge for such a high-speed interface. The routing for such high-speed interface is accomplished under complex set of electrical and layout implementation constraints.

    Allegro PCB Editor has added several new capabilities to improve designers’ productivity and accelerate timing closure. These include ‘adding ground current return path vias to differential pairs during Add Connect’, ‘creating off-angle routes to avoid FR4 fiber weave coupling and achieve better impedance control’, ‘improved arc support in routing’, and many others.


    There is auto-connect routing where a designer can select a set of signals and the route engine creates flow automatically. The ‘Adjust Spacing’ capability allows users to compress spreading of traces in the trunk of a set of signals.


    There is a powerful shape editing environment to quickly create and modify shapes and save lot of time in designing power delivery networks and other complex layout editing. Designers can add notches, join edges, slide edges with corners, move multiple segments with one command, convert corners, and so on.

    Overall Allegro 16.6-2015 portfolio provides a powerful and ideal PCB design platform for modern day PCB designs that need fast turnaround to meet ever shrinking time-to-market window. To know more read the press release here.

    Visit Cadence at booth #3515 at DAC 2015.

    Pawan Kumar Fangaria
    Founder & President at www.fangarias.com

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    How to Push Mobile to Use PCI Express?

    How to Push Mobile to Use PCI Express?
    by Eric Esteve on 05-24-2015 at 7:00 am
    Categories: IP, Synopsys

    By offering low-power PCI Express PHY solution for mobile application! To make it clear, we are not talking about Mobile Express (M-PCIe), but clearly about PCI Express protocol, including a PCIe Controller and a PCIe PHY. Initially developed to support internal connection between the CPU and the GPU in a PC, the technology has been incredibly successful and pervasive. When a new PCIe generation is released, like gen-3 at the end of 2010, the early adopters are searching for maximum performance, like in server, networking or storage applications. High performance associated with high power consumption, but the power is not the primary issue for such applications. But low power is definitely a key target for any mobile, battery powered device. By launching a PCIe gen-3 PHY IP specifically designed for low power behavior, offering industry smallest active power (as low as 50 mW per lane at 8 GT/s) as well as standby power (less than 10 mW per lane), Synopsys clearly target mobile systems like Ultrabook or Tablet.

    PPA: Power, Performance and Area are the IP’s keywords. Let’s have a look at this PHY performance first. PCI-SIG has defined PCIe channel performance requirements for PCIe 3.1 technology. The state of art in mixed-signal design implies using these techniques to enhance signal integrity across high loss and bumpy channels and comply with the specification:

    • multi-phase-locked loops (MPLLs),
    • Feed Forward Equalization (FFE),
    • Continuous Time Linear Equalization (CTLE),
    • programmable Decision Feedback Equalization (DFE)

    This low power PCIe 3.1 PHY is said to meet the specification and also provides flexibility and scalability for high-speed SoCs by offering separate Refclk Independent SSC (SRIS), reference clock forwarding and PCI Express architecture aggregation and bifurcation. No doubt that this is a fully compliant PCIe 3.1 PHY, exhibiting the same performance than any other IP. But which makes it unique is power efficiency, let’s look at the active power consumption characteristic: 5 mW per lane and per GT/s.
    This PHY is supporting supply under drive, a novel transmitter design and equalization bypass schemes. Designing PCIe PHY to support a mobile application, typically SSD card to replace HDD for internal storage, means that the PCIe bus will not drive any long interconnect like a backplane in networking, but rather a few cm long lane(s) to connect the internal SSD with the CPU. That’s why it’s possible to bypass equalization for example, and severely reduce poser consumption. Active power consumption is important, but for a mobile device the leakage power is even more important, forcing you to charge the battery even if you don’t intensively use your device!


    The PCI Express specification defines various power states, L0, L1 sub-states and L2 in order to frame different power conditions. It’s important to keep in mind that, if you can design as you wish to lower the power, you will have to comply with one firm requirement: the 100 ms maximum latency or time to come back to a fully working state. You can see on the above table how the various functions are managed (ON, OFF or IDLE) to comply with the various power states. To be able to put OFF a certain function within a design, Synopsys had to use well-known (at least for mobile SoC designers), power gating, power islands and retention cells techniques. Because a PCI Express is made of a PHY and a Controller, the power gating techniques have been exercise both on the Controller and the PHY raw PCS as well as protocol PCS (both in RTL) via Unified Power Format (UPF). In fine, the power savings in the controller with the L1 sub-states and power gating have given up to 95% reduce current.

    Just take an example with this mobile device breakdown. You can see the battery specification of 5.45 Whr, or 19620 Joules. The “usual” PCIe IP targeting enterprise segment exhibit around standby power of 2 mW, as no specific care has been taken to reduce it. This translates into 9% of the 10 days battery life… and this is not the only semiconductor device integrated into this application! When designing for low standby power, you come down to 0.02% of the 10 days battery life.

    One of the PPA is missing: Area. When we speak about area, we think about cost (a direct impact of the die area). This IP has been designed in such a way that it’s not only the industry’s lowest power, but also the unique PCIe 3.1 PHY IP accepting wire bonding. Wire bond is easily translated into cheap package!

    From Eric Esteve from IPNEST

    Posted on

    eSilicon Lyfts Its Game

    eSilicon Lyfts Its Game
    by Paul McLellan on 05-24-2015 at 3:00 am
    Categories: eSilicon, Semiconductor Services

    We have got used to services like Uber and Lyft (at least in cities that are not so anti-consumer as to ban them, I’m looking at you New York. Et vous Paris). But in most of the semiconductor world we are still stuck standing at the side of the road waving our hand helplessly in the hope that the light on that taxi is actually on. Leading the vanguard of changing this is eSilicon. They put the “e” in Silicon, as it were.

    What eSilicon has been doing is taking more and more of their customer interface where traditionally you would need to go through a person, and moving it online so that it is completely automatic. Just like Lyft and ATMs, this has two benefits:

    • the user of the service gets what they want quicker, without having to stand in line and without having to interface with someone who doesn’t add much value and is just a conduit to the information they really want
    • eSilicon’s cost of providing the service is lower and it scales more easily to large numbers of users

    See The Silicon ATM

    eSilicon started with making it possible for customers to track their own projects as they progressed through fab, testing, packaging and so on. They provided real-time design progress and IC delivery tracking, including order history, forecasts and yield data.

    Next up was MPW (multi-project wafer) quoting. By their nature, MPWs contain a lot of designs and so the natural order of things is to require a lot of quotes for a relatively small amount of revenue (MPWs are not used for production orders).

    See Getting an MPW Quote on My iPhone

    They extended this to getting production quotes. These really are genuine quotes, not some sort of estimate that is low-balled to try and get the job. If you sign the quote, eSilicon will honor the pricing and other terms of the contract.

    See Getting a Quote Without Talking to a Salesman

    Next up was making eSilicon’s library of IP accessible and making it possible to do a design with their IP, switch IP in mid-design and more, all online and without having to issue any sort of purchase order. Of course, before you can tapeout the chip, you have to purchase the IP that you have actually ended up using to get the layout dropped in.

    See eSilicon Try IP Before You Buy

    Finally, just a couple of weeks ago, eSilicon introduced design virtualization technology which uses big data analytics to allow optimal selection of IP, process options, temperature ranges, signoff corners and more.

    See Design Virtualization Technology, VMware for ICs

    eSilicon has completely modernized the user interface of all of these tools and brought them together under the name STAR, which stands for Self-service, Transparent, Accurate, Real-time. STAR consists today of four products:

    • STAR Navigator, which allows you to search, select and try IP online
    • STAR Explorer, which allows you to get quotes online, either for MPW shuttles or for volume production
    • STAR Tracker, which allows you to keep track of your design once it enters the production process
    • STAR Optimizer, which is the interface to eSilicon’s design virtualization technology. This checks if a design is optimization-ready and provides an interface to submit the design. Design optimization is provided as an eSilicon service since the procedure is not automatic and requires an expert pilot. It is a jet fighter not an automobile

    I took some of the services out for a spin. As a humble blogger I don’t have a design in progress so I can’t play with the STAR Tracker. But I can at least pretend I have a design and get some quotes.

    First an MPW. Here is the form to provide the data required for the quote.

    If you have used the old MPW quote system you will see that this is a lot cleaner. The forms are dynamic in the sense that, for example, if you select a different foundry then you get a different selection of options.

    The interface for getting a full production quote is more complex. It starts off very similar.

    But there are a lot more fields that will open up for you to fill out. I’m not going to go through the whole thing. You can try it yourself just to see how it works, eSilicon won’t mind. Just get registered if you are not already and you can try any of these services for yourself for free.

    The last tool, the STAR Optimizer, allows you to run a free audit script to determine if your design is clean and optimization ready. If it is then you can simply click a button in the interface and…well, ok, this is the one thing that is not completely automatic. eSilicon will contact you and quote you for the optimization service and then (assuming you accept the quote, obviously) they will do all the optimization runs and give you the information you required. So not quite untouched by human hand in this case. But an interesting twist is that you only pay eSilicon for the service if they can optimize the design as agreed to in the quote you develop with them.

    So there it is. Reach for your mouse and reach for the STARs.

    The eSilicon STAR page, including links to register or login, is here.