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VESA DSC Encoder Enables MIPI DSI to Support 4K resolutions

VESA DSC Encoder Enables MIPI DSI to Support 4K resolutions
by Eric Esteve on 11-08-2017 at 12:00 pm

Some of the MIPI specifications are now massively used in mobile (smartphone), like the Multimedia related specs, Camera Serial Interface (CSI-2) and Display Serial Interface (DSI). These specifications are now adopted inautomotive infotainment systems, and augmented reality (AR)/ virtual reality (VR) devices. If you look at the picture below (MIPI Ecosystem survey 2015), MIPI DSI and the associated D-PHY are seeing a very high adoption level in mobile phone. We know that pervasion is strong beyond mobile: automotive or AR/VR.

But displays for these applications are becoming more sophisticated with quad HD or 4K resolutions at faster frame rates and support for RGB formats. This evolution has introduced new challenges for designers – managing the required data bandwidth while reducing power consumption and without compromising visual quality. Designers need a protocol that enables visually lossless compression over display interfaces like MIPI® Display Serial interface (DSI®).


The Video Electronics Standards Association (VESA) Display Stream Compression (DSC) standard offers visually lossless performance and low latency for ultra-high-definition (UHD) displays. VESA has collaborated with the MIPI Alliance to get the DSC standard adopted into the MIPI DSI standard. The challenge is to enable higher resolution, like 4K displays, which would require higher bandwidth, while keep using the mature, production proven MIPI D-PHY specification. MIPI DSI operates on the MIPI D-PHY physical link at 2.5 Gbps per four lanes yielding a maximum data rate of 10 Gbps per link. However, as outlined below, high-end video and image resolutions such as 4K and 3D 1080p require higher bandwidth:

– 4K: 24-bit RGB @ 60 frames per second (FPS) requires 13 Gbps (12 Gbps for active area)
– 3D 1080p: 24-bit RGB @ 60 FPS requires 12 Gbps (11 Gbps for active area)


For deeper color modes, bandwidth requirements are even higher, creating a problem that would normally require designers to increase DSI data lanes by re-architecting devices and redesigning circuits, which results in higher design time, cost and risk.

The solution came from VESA, defining Display Stream Compression (DSC) algorithm and the collaboration between MIPI and VESA has allowed incorporating DSC into DSI. According with VESA, DSI encapsulation into DSC protocol has provided “designers of source and display devices [with] a visually lossless, standardized way to transfer more pixel data over display links and to save memory size in embedded frame buffers in display driver ICs.” The Figure below shows a block diagram of VESA DSC integrated into MIPI DSI:


The VESA DSC algorithm can compress data in constant bit rate mode, providing a deterministic size stream that can be transported by DSI without further processing or padding. With VESA DSC, 4K and 3D 1080p video and image resolutions are now possible over existing display links.

– 4K, compressed to 12 bpp @ 60 FPS requires 6.5 Gbps –> 3 or 4 lanes- 4K, compressed to 8 bpp @ 60 FPS requires 4.4 Gbps –> 2, 3 or 4 lanes

– 3D 1080p, compressed to 12 bpp @ 60 FPS requires 6 Gbps –> 3 or 4 lanes
– 3D 1080p, compressed to 8 bpp @ 60 FPS requires 4 Gbps –> 2, 3 or 4 lanes

How to implement this compression? Before compression, an image is divided into a grid of slices. A DSC encoder, which can be made up of multiple cores that operate in parallel, applies compression to each slice independently. The next picture shows an example of how DSC cores can compress 4K image efficiently. The DSC encoder in this example (on the left) includes four cores and the image (on the left) is split into 4 columns by 15 rows, and each resulting slice is compressed by the corresponding DSC cores (indicated by color) in parallel.


Unlike compression standards such as H.264 or H.265, DSC does not use inter-frame compression, it offers very low latency and reduced memory size. DSC’s compression algorithm was designed to be implemented in hardware without the need for multimedia processors, making it highly efficient for area and power in SoCs.

Visually lossless compression is the ideal method to enable quad HD or 4K resolution embedded displays in high-end smart phones, automotive infotainment systems and AR/VR devices. The VESA DSC standard helps designers overcome bandwidth limitations associated with MIPI D-PHY without costly and risky circuit redesign. VESA DSC is an emerging standard that delivers visually lossless compression, providing designers flexible, low-latency, low-memory, and error-resilient results.

Synopsys has integrated VESA DSC into its silicon-proven DesignWare® MIPI DSI IP to enable quad HD or 4K resolution displays.

You can look at this articlefrom Synopsys, precisely describing how DSC and DSI can be implemented.

From Eric Esteve from IPnest


DesignShare is all About Enabling Design Wins!

DesignShare is all About Enabling Design Wins!
by Daniel Nenni on 11-08-2017 at 7:00 am

One of the barriers to silicon success has always been design costs, especially if you are an emerging company or targeting an emerging market such as IoT. Today design start costs are dominated by IP which is paid at the start of the project and that is after costly IP evaluations and other IP verification and integration challenges. Given that, reducing design costs and enabling design starts has always been a major industry focus starting with the fabless semiconductor transformation that began 30 years ago, which brings us to the DesignShare announcement made by SiFive and Flex Logix last week.

As an emerging IP company one of the greatest challenges is getting customers comfortable with your IP, your support model, and your company in general. Nobody knows this better than Andy Jaros, Vice President of Sales at Flex Logix. Andy started his semiconductor career with Motorola, followed by ARM, then ARC which is where I met him. Virage Logic acquired ARC in 2009 and Andy assumed a leadership role which continued for five years after Synopsys acquired Virage in 2010. Andy has been enabling design starts for most of his career so he knows IP.

I caught up with Andy at ARM TechCon last month and talked about the SiFive DesignShare program. Flex Logix joined DesignShare so customers can get customized chip prototypes with eFPGA cores at a very low cost because Flex Logix and other DesignShare participants defer IP costs until the customer is ready to go into production. Needless to say, Andy is 100% behind this program as it will allow him to work with a much wider range of design starts in a much more efficient manner, for the greater good of the semiconductor industry, absolutely.

By the way, I found the new Flex Logix website to be one of the best IP company websites in regards to content and user friendliness, check it out.

“There is a critical need in the chip industry to provide a faster, cheaper way for innovative companies to rapidly prototype new, advanced chip architectures,” said Geoff Tate, CEO of Flex Logix. “Through DesignShare, SiFive and Flex Logix can give customers a highly programmable, flexible chip design for both microcontroller SoCs and multicore process SoCs. The RISC-V architecture provides excellent performance, and – when combined with embedded FPGA functionality, can provide higher performance in a reconfigurable way.”

Geoff Tate (founding CEO of Rambus) is one of the more interesting and more available IP CEO’s you can meet. He attends as many conferences as I do and is eager to interact with customers and partners. You can meet Geoff and the Flex Logix team next at the REUSE 2017 Conference on December 14[SUP]th[/SUP].

“The addition of Flex Logix’s best-in-class embedded FPGA platform to the DesignShare ecosystem provides engineers with a new and better way to bring SoCs to market,” said Naveed Sherwani, CEO of SiFive. “The adoption of the RISC-V architecture continues to experience significant growth, and the addition of embedded FPGA technologies through DesignShare will make it easier and more flexible for designers to employ RISC-V in their future designs across a wide range of implementations, from embedded devices to the data center.”

Naveed Sherwani is another friendly semiconductor CEO that attends many of same events I do. He has founded or cofounded 9 different companies including Open-Silicon and is quite the semiconductor historian.

Bottom line:
Design starts are the lifeblood of the semiconductor industry and we should all do whatever is possible to enable them and DesignShare does just that.


12 Year-old Semiconductor IP and Design Services Company Receives New Investment

12 Year-old Semiconductor IP and Design Services Company Receives New Investment
by Daniel Payne on 11-07-2017 at 12:00 pm

I have a transistor-level IC design background so was intrigued to learn more from the CEO of an IP and services company that started out in India 12 years ago. Last week I spoke with Samir Patel, CEO of Sankalp Semiconductorabout the newest $5 million financial investment in his company from Stakeboat Capital Fund. The Stakeboat Capital Fund has some 28 years of investing experience and a current market capitalization above $8B.

I knew that the general trend was for IP companies to provide more specialized content along with design services to help speed new electronic products to market, but I didn’t realize that there are some 200 IC design services companies around the world competing for this growing market segment. What makes outsourced IC design services attractive to OEMs are:

  • Lower cost of development than hiring and training new engineers
  • Lower risk with a supplier that has a good track record
  • Access to analog and mixed-signal IP blocks

Related blog – ARM’s back in FD-SOI. NXP’s showing real chips

Sure, there are giants in outsourcing like Wipro and Infosys, so what makes Sankalp interesting to me is their focus on analog and mixed-signal IP, something that is in strong demand these days as every IoT device with a sensor will require an AMS chip to get data into a digital format. The engineers at Sankalp have quite a broad range of experience to help speed the AMS parts or all of your next chip projects:

  • Specification definition
  • RTL design and verification
  • SoC Implementation
  • IP blocks
  • AMS design
  • Custom layout and P&R
  • Technology Foundry Interface
  • Validation and Characterization

Related blog – Can FD-SOI Change the Rules of the Game?

The success at Sankalp can be measured by the staff size with some 600 employees worldwide, serving tier one semiconductor companies. They can work with any foundry partner that you choose.

I learned that their logo shows two hands above a fire, and that Sankalp is a Sanskrit word meaning an oath or resolve. Instead of starting up the company in Bangalore, they located outside of Bangalore closer to engineering colleges and where they could train new hires at a lower cost and have lower attrition. TI was an early anchor client for them. Global locations include:

  • India
    • Noida
    • Kolkata
    • Bhubaneswar
    • Hubli
    • Bangalore
  • Franfurt, Germany
  • Ottawa, Canada
  • Sunnyvale, CA
  • Dallas, TX

Related blog – IP/SoC Rebound in 2015!

I did ask about exit plans or getting acquired by a larger firm, and was refreshed to hear that they will continue to grow and invest in their own success instead of cashing out. Past acquisitions include Interra SSG and KPIT SSG. Mr. Patel previously started up the RAMBUS design center in India, so really knows the semiconductor design industry. One new acronym that I heard for the first time was Application Specific System on a Chip (ASOC). I found Samir’s photo online and felt connected to him because we both have some grey hair and have followed the semiconductor industry for decades.

 


Webinar: High-Capacity Power Signoff Using Big Data

Webinar: High-Capacity Power Signoff Using Big Data
by Bernard Murphy on 11-07-2017 at 7:00 am

Want to know how NVIDIA signs off on power integrity and reliability on mega-chips? Read on.

PPA over-design has repercussions in increased product cost and potential missed schedules with no guarantee of product success. Advanced SoCs pack more functionality and performance resulting in higher power density, but traditional approaches of uniformly over-designing the power grid which have worked in the past are no longer an option with severely constrained routing resources. To add to these problems, there are hundreds of combinations of PVT corners to consider for each of an increasing number of verification objectives.

REGISTER HERE for the webinar on Tuesday Nov 14[SUP]th[/SUP] at 8am PST

For example, an ADAS SoC is used for a variety of applications such as pedestrian detection, parking assist, vehicle exit assist, night vision, blind spot monitoring, collision avoidance, and a whole lot more. The numbers of vectors designers need to run simulations for have increased enormously. It is nearly impossible to uncover potential design weaknesses when you are simulating only a handful of vectors for just a fraction of second. How do you ensure you have enough design coverage?

Power grid design has become a limiting factor for achieving the desired performance and area targets in next generation SoCs. Sharper slew rates, higher current densities and faster switching speeds pose significant challenges to power integrity and reliability signoff. Lower operating voltages lead to tighter noise margins, resulting in a chip that is very sensitive to changes in supply voltage. Higher device density and longer wires in these advanced designs lead to increased node count by at least an order of magnitude posing significant capacity and performance challenges for traditional EDA tools to address.

As design size increases, turnaround time for solving billion-plus instance designs becomes critical. Next generation SoC power integrity and reliability signoff solution should scale elastically with capacity and performance. It is imperative to iterate designs over multiple operating conditions and scenarios rapidly, with an overnight turnaround time to maximize design coverage. Also, it is equally important to gain key insights from these large design databases to prioritize design fixes.

In this webinar, learn how NVIDIA has developed a workflow to run a flat, full-chip power integrity and reliability signoff analysis using a fully distributed compute and big data solution with ANSYS RedHawk-SC. They achieved a turn-around time of well under 24 hours for full-chip flat power signoff analysis on NVIDIA’s largest GPU – Volta, which contains around 21 billion transistors.

Additionally, silicon correlation exercises performed on the Volta chip using RedHawk-SC produced simulated voltage values that were within 10 percent of silicon measurement results. Discover how NVIDIA’s most powerful GPU uses ANSYS’ next generation SoC power signoff solution based on big data to deliver the best performance for cutting-edge AI and machine learning applications.

REGISTER HERE for the webinar on Tuesday Nov 14[SUP]th[/SUP] at 8am PST

About Ansys
If you’ve ever seen a rocket launch, flown on an airplane, driven a car, used a computer, touched a mobile device, crossed a bridge, or put on wearable technology, chances are you’ve used a product where ANSYS software played a critical role in its creation. ANSYS is the global leader in engineering simulation. We help the world’s most innovative companies deliver radically better products to their customers. By offering the best and broadest portfolio of engineering simulation software, we help them solve the most complex design challenges and engineer products limited only by imagination.


Webinars: Bumper Pack of AMS Webinars from ANSYS

Webinars: Bumper Pack of AMS Webinars from ANSYS
by Bernard Murphy on 11-06-2017 at 12:00 pm

Power integrity and reliability are just as important for AMS designs as they are for digital designs. Ansys is offering a series of five webinars on this topic, under a heading they call ANSYS in ACTION, a bi-weekly demo series from ANSYS in which an application engineer shows you how simulation can address common applications. Schedule a few 20-minute breaks to see how Ansys can solve your problems.


You can REGISTER HERE for any or all of these webinars.

November 16[SUP]th[/SUP] 2017 at 10AM PST The first webinar in the series is on Analog and Mixed Signal Workflows for Power and Reliability Signoff for SerDes IP and PMIC. Analog and mixed signal IPs are very complex and require significant time to design, verify and validate. With increasing mask costs and tighter design cycles, first time silicon success is key to accelerate time to market and beat the competition. Join us for this 20-minute webinar to learn how AMS workflows based on ANSYS Totem, a layout-based transistor level power and reliability signoff platform, can enable you to design the next generation of SerDes IP or PMIC for cutting-edge applications.

November 30[SUP]th[/SUP] 2017 at 10AM PST The second webinar in the series is on Enabling Early Power and Reliability Analysis for AMS Designs. Attend this webinar to discover the benefits of doing early power and reliability analysis with just a GDS layout. This presentation will demonstrate early IP level connectivity checks; missing via checks; point to point resistance and short path resistance checks; and early static analysis to identify structural design weaknesses using ANSYS Totem’s rich GUI interface.

December 7[SUP]th[/SUP] 2017 at 10AM PST The third webinar in the series is on Enabling Power and Reliability Signoff for AMS Designs. Attend this webinar to learn how ANSYS Totem can model and simulate the required power and reliability signoff checks for AMS designs. This presentation will demonstrate the benefits of using Totem to perform dynamic voltage drop and EM checks through its rich GUI interface, which can also be leveraged for debugging purposes.

December 14[SUP]th[/SUP] 2017 at 10AM PST The fourth webinar in the series is on Enabling FinFET Thermal Reliability Signoff for IPs. ANSYS Totem can solve the challenges faced by engineers trying to ensure thermal and electromigration (EM) reliability in advanced IPs. Join this webinar to see a demonstration of self-heat analysis on an IP test case using ANSYS Totem’s rich GUI interface. The demonstration will cover flow setup, debugging and result exploration for reliability signoff.

January 11[SUP]th[/SUP] 2018 at 10AM PST The fifth webinar in the series is on Enabling ESD Reliability Signoff for AMS IPs. Attend this webinar to discover how ANSYS PathFinder can help you solve the challenges you face in trying to ensure ESD robustness in today’s AMS IPs. Watch a live demonstration of ANSYS PathFinder on an IP-level test case to highlight the benefits of a layout-based ESD integrity solution for resistance and current density checks.

REGISTER HERE for any or all of these webinars.

About Ansys
If you’ve ever seen a rocket launch, flown on an airplane, driven a car, used a computer, touched a mobile device, crossed a bridge, or put on wearable technology, chances are you’ve used a product where ANSYS software played a critical role in its creation. ANSYS is the global leader in engineering simulation. We help the world’s most innovative companies deliver radically better products to their customers. By offering the best and broadest portfolio of engineering simulation software, we help them solve the most complex design challenges and engineer products limited only by imagination.


TSMC EDA 2.0 With Machine Learning: Are We There Yet ?

TSMC EDA 2.0 With Machine Learning: Are We There Yet ?
by Alex Tan on 11-06-2017 at 7:00 am

Recently we have been swamped by news of Artificial Intelligence applications in hardware and software by the increased adoption of Machine Learning (ML) and the shift of electronic industry towards IoT and automobiles. While plenty of discussions have covered the progress of embedded intelligence in product roll-outs, an increased focus on applying more intelligence into the EDA world is required.

Earlier this year TSMC reported successful initial deployment of machine learning on ARM A72/73 cores in which it helps predict an optimal cell clock-gating to gain overall chip speeds of 50 – 150 MHz. The techniques include training models using open source algorithms maintained by TSMC.


In ISPD 2017
,TSMC referred to this platform as the ML Design Enablement Platform. ​It was anticipated to allow designers to create custom scripts to cover other designs.

During the
2017 CASPA Annual Conference, Cadence Distinguished Engineer, David White shared his thoughts on the current challenges faced by the EDA world which consists of 3 factors:

  • Scale – with increasing design sizes, more rules/restrictions and massive data such as simulation, extraction, polygons, technology files are expected.
  • Complexitymore complex FinFET process technologies resulting in complicated DRC/ERC, while pervasive interactions between chip and packaging/ board becoming the norm. On the other hand thermal physical effect between devices and wires is needing attention.
  • Productivityintroduce uncertainty and more iterations while limited retrained design and physical engineers.

Furthermore, David categorized the pace of ML (or Deep Learning) adoption into 4 phases:


Although the EDA industry has started embracing ML as a new venue to enhance their solutions this year, the question is: How far have we gone? During 2017 Austin DAC, several companies announced augmenting ML in their product offerings as shown in table 2.


You might have heard the famous quote, “War is 90% information“. ML adoption may require good data analytics as one is faced with paramount data size to handle. For most hardware products augmenting ML can be either done on the edge (gateway) or in clouds. With respect to the EDA tools, it also becomes a question of how massive and accurate the trained models need to be and whether it requires many iterations.

For example, predicting the inclusion of via pillar in a FinFET process node could be done at a different stage of design implementation while the model accuracy should be validated at post-route. Injecting them during placement would be different than in physical synthesis where there is still no concept of legalized design and projected track usage.

Let’s revisit David’s presentation and find out what steps are required to design and develop intelligent solutions which involve harnessing ML, analytics and clouds, coupled with prevailing optimizations. He believes it’s comprised of two phases: training development phaseand operational phase.Each implies certain context as shown in the following snapshot (training = data preparation + model based inference; operational = adaptation).


The takeaways from David’s formulation involve properly managing data preparation to reduce its size prior to generating, training, and validating the model. Once completed, the calibration and integration to the underlying optimization or process can take place. He believes that we are just starting phase 2 in augmenting ML into EDA (refer to table 1).

Considering the increased attention given to ML during 2017 TSMC Open Innovation Platform, in which TSMC explored the use of ML to apply path-grouping during P&R to improve timing and Synopsys MLadoption to predict potential DRC hotspots, we are on the right track to have smarter solutions to balance the complexity challenges to high density and finer process technology.


Deep Learning and Cloud Computing Make 7nm Real

Deep Learning and Cloud Computing Make 7nm Real
by Daniel Nenni on 11-05-2017 at 7:00 am

The challenges of 7nm are well documented. Lithography artifacts create exploding design rule complexity, mask costs and cycle time. Noise and crosstalk get harder to deal with, as does timing closure. The types of applications that demand 7nm performance will often introduce HBM memory stacks and 2.5D packaging, and that creates an additional long list of challenges. So, who is using this difficult, expensive technology and why?

A lot of the action is centering around cloud data center buildout and artificial intelligence (AI) applications – especially the deep learning aspect of AI. TSMC is teaming with ARM and Cadence to build advanced data center chips. Overall, TSMC has an aggressive stance regarding 7nm deployment. GLOBALFOUNDRIES has announced 7nm to support for, among other things, data center and machine learning applications, details here. AMD launched a 7nm GPU with dedicated AI circuitry. Intel plans to make 7nm chips this year as well. If you’re wondering what Intel’s take is on AI and deep learning, you can find out here. I could keep going, but you get the picture.

It appears that a new, highly connected and automated world is being enabled, in part, by 7nm technology. There are two drivers at play that are quite literally changing our world. Many will cite substantial cloud computing build-out as one driver. Thanks to the massive, global footprint of companies like Amazon, Microsoft and Google, we are starting to see compute capability looking like a power utility. If you need more, you just pay more per month and it’s instantly available.

The build-out is NOT the driver however. It is rather the result of the REAL driver – massive data availability. Thanks to a new highly connected, always-on environment we are generating data at an unprecedented rate. Two years ago, Forbes proclaimed: “more data has been created in the past two years than in the entire previous history of the human race”. There are other mind-blowing facts to ponder. You can check them out here. So, it’s the demand to process all this data that triggers cloud build-out; that’s the core driver.

The second driver is really the result of the first – how to make sense out of all this data. Neural nets, the foundation for deep learning, has been around since the 1950s. We finally have data to analyze, but there’s a catch. Running these algorithms on traditional computers isn’t practical; it’s WAY too slow. These applications have a huge appetite for extreme throughput and fast memory. Enter 7nm with its power/performance advantages and HBM stacks. Problem solved.

There is a lot of work going on in this area, and it’s not just at the foundries. There’s an ASIC side of this movement as well. Companies like eSilicon have been working on 2.5D since 2011, so they know quite a bit about how to integrate HBM memory stacks. They’re also doing a lot of FinFET design these days, with a focus down to 7nm. They’ve recently announced quite a list of IP targeted at TSMC’s 7nm process. Here it is:

Check out the whole 7nm IP story. If you’re thinking of jumping into the cloud or AI market with custom silicon, I would give eSilicon a call, absolutely.


Choosing the lesser of 2 evils EUV vs Multi Patterning!

Choosing the lesser of 2 evils EUV vs Multi Patterning!
by Robert Maire on 11-03-2017 at 12:00 pm

For Halloween this week we thought it would be appropriate to talk about things that strike fear into the hearts of semiconductor makers and process engineers toiling away in fabs. Do I want to do multi-patterning with the huge increase in complexity, number of steps, masks and tools or do I want to do EUV with unproven tools, unproven process & materials and little process control?
Continue reading “Choosing the lesser of 2 evils EUV vs Multi Patterning!”


Effective Project Management of IoT Designs

Effective Project Management of IoT Designs
by Mitch Heins on 11-03-2017 at 7:00 am

ClioSoft is well known for their SoC design data management software SOS7 and more recently for their IP reuse ecosystem called designHUB. What is less known is how designHUB enables design teams to collaborate efficiently and better manage their projects by keeping everyone in sync during development. Not only does it provide a platform for design teams to more easily integrate IPs into their designs and collaborate more efficiently, but it also enables cooperation among diversified groups that normally would not work that closely together. This is an essential element of project management for complex systems-on-chip (SoC) and systems-in-a-package (SiP) designs.

With the advent of the Internet-of-Things (IoT), systems are becoming much more complex as they use heterogeneous system architectures both on the SoC and within a package. These systems can have multiple different CPU cores, hardware accelerators, memories, network-on-chip (NoC) fabrics and numerous peripheral interfaces. Added to this are the complexities of the package, interposer and production board, not to mention boards designed for silicon bring-up and for prototyping. IoT system projects can have hundreds of engineers with different backgrounds and expertise working on them. The question then becomes how to manage and coordinate efforts between system designers, software engineers, IC designers, package and interposer designers, design-for-manufacturing (DFM), design-for-test (DFT) and test engineers.

ClioSoft’s designHUB turns out to be an excellent platform to bring these diverse groups together. When design data management is discussed we tend to gravitate to the various design data formats that needs to be shared between groups. We forget however that there is a much larger set of data represented by the knowledge base of the engineers that create the design. Additionally, for any given function, there is meta data about the function such as specifications, verification methodologies, test methodologies and manufacturing assumptions to which that function is being designed. This is true whether you are designing hardware logic, embedded software, NoCs, or last-level cache memories for the system. ClioSoft’s designHUB provides a rich environment that allows data of any form to be documented, versioned, stored, linked to other dependent data, searched and retrieved.

The unique thing about designHUB is that it provides a dashboard that tracks all activities in which an engineer is involved. The dashboard gives each designer a customized experience that can be set up to notify them upon specific events that may impact their work.

As an example, if a software developer is writing a device driver that is dependent upon some custom logic, and details for that custom logic are changed, designHUB can be set up to instantly notify the software developer of the changes. The software developer would have access to a knowledge base for the design part in question, where they could get details about the changes that occurred. Similarly, impacts to the developer’s code may propagate on to system test engineers who are working on the modules that will be used to validate the device driver once parts are back from manufacturing. Schedule changes can also be propagated to those with dependencies as well as to a master schedule that is reviewed by project management.

ClioSoft’s designHUB also has a social media component to it that allows for crowdsourcing type interactions. Open questions can be asked of the project with anyone in the project being able to share their insights and knowledge. All knowledge shared becomes part of the knowledge database for the project as well as for the part of the design that is being discussed. Some subjects such as verification and test tend to cut widely across a project. Proposed changes in these types of areas can be quickly discussed. Management can also play a part in these discussions enabling fast decision making and easier dissemination of policy changes to project team members using the communications capabilities of designHUB.

The best part of all this interaction is that the conversations and data are preserved for the next revision of the project or for derivative designs that may use parts of the current project. Not only is the basic design data stored and versioned, but also the meta data about the design including dependency relationships between different modules. This means that project managers can track the impact of proposed changes to modules to gauge the impact of a desired change and to check that affected areas are indeed re-verified to ensure the new changes have not inflicted collateral damage in other parts of the project. In addition, if a designer leaves the company the design knowledge remains captured within designHUB thereby protecting the company from any major problems.

Lest this sound a little too open or lacking in controls, rest assured that you can also use designHUB to enable workflows with approval and signoff procedures for the various design objects such as IPs, documents etc.. ClioSoft’s designHUB can also track time through various project phases which can later be used for post tape-out lessons-learned reviews. The idea here is to make decisions as transparent as possible without giving way to total anarchy. Projects are still “managed” but it becomes much easier for management and engineering teams to make informed decisions and to stay abreast of changes being made to the project that might affect them.

All in all, designHUB is a great suite of tools that is only just beginning to see reveal some of its features and use models. For now, we can check off IP management and Project management. It will be interesting to see what users come up with next.

See also:
ClioSoft designHUB web page
ClioSoft designHUB webinar


Using a TCAD Tool to simulate Electrochemistry

Using a TCAD Tool to simulate Electrochemistry
by Daniel Payne on 11-02-2017 at 12:00 pm

In college I took courses in physics, calculus, chemistry and electronics on my way to earn a BSEE degree, then did an 8 year stint as a circuit designer, working at the transistor level and interacting with fab and test engineers. My next adventure was working at EDA companies in a variety of roles. As a circuit designer I knew that we had software tools like SPICE to help us simulate the timing, power, currents and detailed operation of transistor devices, cells, blocks and modules. What I’ve come to learn about is that device technology engineers also need software tools to help them simulate electrical, chemical, optical and thermal behavior of semiconductor devices. Silvaco recently held a webinar on Wednesday, so I attended to learn about TCAD Simulation of Ion Transport and Electrochemistry.

Very quickly I learned the definition of Electrochemistry by our presenter Dr. Carl Hylin.
Electrochemistry describes the chemical interactions between electrons, holes, ions and uncharged chemical species.

I felt pretty comfortable as an EE to hear familiar terms like electrons, holes and ions, but chemical species was a new term for me. There are at least four major applications where knowing what is happening at the electrochemical level is mandatory:

 

  • Standard semiconductor devices
    • Shockley-Read-Hall (SRH) recombination
    • Auger recombination
    • Charge trapping
  • Displays
    • Degradation in amorphous TFTs
  • Spacecraft electronics
    • Enhanced low-dose-rate sensitivity
  • Non-volatile memories (RRAM), solid state batteries
    • Ion transport and charge storage

     

Silicon, Germanium, Gallium and Arsenide materials are all examples of a chemical species. Equations have been derived that define how chemical species behave, and that forms the basis for apply software like the Silvaco simulator called Victory Device:

When using the Victory Device tool you first define the materials (species) and then the type of reaction you want to simulate. For example if you wanted to model and simulate the compound semiconductor made up of Indium, Gallium and Zinc (InGaZn) using Victory device then it’s only a few lines of coding, shown below in colored letters:

With this device simulator you can define as many species as needed, and you get to define the names of the species in terms that are self-documenting. Doping levels are also defined, along with the interface between species, so here’s another example using two chemical species: Silicon (Si) and Hydrogen (H).

For our example of SiH we also define properties like diffusivity and the maximum species concentration, with units of atoms/cm^3 :

Silicon is a fixed species, meaning that the diffusivity is zero, however Hydrogen has a non-zero diffusivity and is transportable. Here’s a Lewis diagram showing Hydrogen on the left and Si plus SiH on the right:

Mobile species can hit a boundary and be blocked, so that there’s no transport. In Victory Device you define at what concentration level a species may transport, here’s an example with Hydrogen using a fixed concentration amount:

To model and simulate the passivated interface degradation with the SiH material it takes just 16 lines of code in Victory Device:

The results of simulation can be viewed in a couple of ways, wither a structured file output or a log file output. The final example from the webinar was showing Victory Device was used for predicting the negative bias stress simulation with illumination in a TFT made up of Indium, Gallium, Zinc and Oxide. Simulation results correlated well with published data, this graph shows the Vt shift by NBIS for a 20nm IGZO TFT device where red curves are measured results and blue is from simulation:

With device simulation there are always more demands, so the engineers at Silvaco are adding new abilities to their road map for Victory Device, like:

  • Constant surface velocity and constant flux boundary conditions
  • Vacancies
  • Thermochemistry
  • Steady-state simulation
  • Added reaction models
  • Added mobility models
  • Improved automatic time-step control

Summary
In the old days the device technology engineer would make many physical experiments, wait for the wafers to get through the line, then make measures to decide if more iterations were required before reaching a stable process. With the advent of TCAD tools like Victory Device we can now perform many device simulations in a virtual world based on the laws of physics and chemistry, thus shortening time to market and creating a more reliable semiconductor process.

To replay the entire 45 minute webinar you may register online now.

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