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April 23, 2020December 27, 2023

Wi-Fi Bulks Up

Wi-Fi Bulks Up
by Bernard Murphy on 04-23-2020 at 6:00 am
Categories: Ceva, IP
4 Comments

Wireless discussion these days seems to be dominated by 5G, but that’s not the only standard that’s attracting attention. The FCC just circulated draft rules to dramatically expand bandwidth available to Wi-Fi in the new Wi-Fi 6e standard.

Is this a tragic plea for attention from a once-important standard, now eclipsed by its cellular big brother? Not at all. According to Cisco, 60% of mobile traffic will be offloaded to Wi-Fi by 2022. That’s both an opportunity and a challenge. The challenge comes in bandwidth.

Vanilla Wi-Fi at 2.4GHz is competing with other standards like Bluetooth and ZigBee (and garage-door openers). It’s become a crowded space. In 2014, Wi-Fi 5 (then more cryptically known as 802.11ac) appeared, offering more bandwidth at 5GHz – that other option on your home router. But that band is also getting crowded because we’re pushing more through our internet connections (e.g. streaming video). WI-Fi 6 added to the noise in 2019.

Where’s all that mobile traffic going to go? Onto a new band at 6GHz, with 1200MHz of bandwidth is where. This will be called Wi-Fi 6e and should fix an important limitation in Wi-Fi 6 – practically attainable bandwidth. I should add here that 6e is not a new standard, it is simply an expansion of range.

In principle the 6 standard offers bandwidth options up to 160MHz, in practice that high-end option has never been very useful thanks to interference from other traffic. So when you’re wandering around an airport (remember those days?), Wi-Fi access points are more likely configured to one of five 80MHz bands. There’s no loss in net available bandwidth but you don’t have access to fat 160MHz pipes.

The 6e standard will have 1200MHz total bandwidth, offering up to seven 160MHz bands and fourteen 80MHz bands. In total, this increases available bandwidth for Wi-Fi by almost a factor of 5.

One place this added capacity will be appreciated in in wireless VR/AR headsets. Today those run on an earlier Wi-Fi standard called WiGig, starting at 60GHz. Loads of bandwidth, very low latency but extremely power hungry and must be built in specialized processes, also making them expensive. 6e won’t be able to offer the same extreme performance but is viewed as still good enough, at much lower power and can be build in mass market mobile processes, i.e. much more cheaply.

Wi-Fi 6e will have a little shorter range than Wi-Fi 6 and power will be a little bit higher. For access points (APs) in airports, stadiums and our homes, that shouldn’t be a big problem. We will need some more APs to provide decent coverage and our phone charge will run down a little more quickly but not very noticeably.

Wireless chips are already being built, from Qualcomm and Broadcom, though the certification still hasn’t been announced. I’ve seen that Intel are also planning to release a chip later in the year. So I’m guessing Wi-Fi 6e-enabled products aren’t likely to appear before late 2020 or early 2021.

Wireless IP to take advantage of Wi-Fi 6E will be essential for those who want to jump on this bandwagon. CEVA tells me that this will only require a simple upgrade in its RivieraWaves 802.1ax IP (you’ll need some work in the RF stage as well). The IP will be released as soon as the standard is ratified. You can learn more about RivieraWaves Wi-Fi HERE.

Also Read:

5G Infrastructure Opens Up

Using IMUS and SENSOR FUSION to Effectively Navigate Consumer Robotics

A Bundle of Goodies in Bluetooth 5.2, LE Audio

April 22, 2020August 9, 2020

ASML A Scenario More Lumpy While Demand and Tech Remain Solid Despite Covid Delays

ASML A Scenario More Lumpy While Demand and Tech Remain Solid Despite Covid Delays
by Robert Maire on 04-22-2020 at 2:00 pm
Categories: Foundries, Lithography, Semiconductor Advisors, Semiconductor Services

Covid issues create “lumpy” quarters due to delays
Orders & demand remain solid and strong
2020 Year financials intact so far but ignore Qtrs
Taking prudent actions- no buybacks or guidance

As expected, Covid impacts both shipments & supply chain, ignore the near term lumpiness…
ASML reported revenues of Euro 2.4B and EPS of Euro 0.93 per share, obviously well short of prior expectations set before Covid19.

The results were impacted by the loss of Euro 200M of DUV sales and Euro 500M of EUV sales due to issues primarily related to Covid19 related delays and interruptions. There were issues both with the supply chain to build tools as well as getting tools delivered. It seems the part in the middle, manufacturing, was spared significant impact.

In our view investors have to take a deep breath and ignore near term and quarterly results as large lumps of revenue will flow in and out of quarters while Covid19 issues still exist.

We are much better off focusing on order rates and yearly goals of tool shipments and ramping of new technology than counting revenue in a specific quarter.

Order intake was a very solid Euro 3B and the company maintains its goal of 35 EUV systems in 2020. High NA has not changed so we view the overall long term story as very much intact.

Business will remain lumpy given EUV pricing…
When tools cost over Euro 100M each, a couple of tools slipping in or out of a quarter can make things look exceedingly good or bad. As EUV becomes a bigger percentage of business over time this lumpiness will continue. This time the shifting of revenues was caused by a pandemic, next time it could be some other global or trade related event that was just as unseen as Covid19 was 3 months ago.

From a short term investor perspective we think it would be natural to take advantage of this variability by buying into light quarters and selling into inflated quarters.

Obviously, long term investors just have to sit back and focus on order intake, backlog, annual goals and shipments and technology progress.

It would be incorrect to assume that just because there is a long lead time and large backlog that ASML can manage tool delivery or build times during such global disturbances.

Taking prudent steps…
As we have heard from a number of other companies ASML is stopping share buy backs and more conservatively managing cash by slowing expenses and hires. This is nothing more than correct behavior and not an indication of expectations.

It would also be prudent at this time to use cash to help manage the supply chain with existing and new suppliers to maintain a flow of materials, which ASML is doing.

Q2 up 50%????
Even though the company is not giving “official” guidance they are softly guiding to sales recognition being up 50% in Q2 as systems get recognized and impacts of some delays get worked out.

Obviously, just as we would ignore Q1 weakness we would also ignore a 50% rise in Q2 as tools pushed out of Q1 into Q2.

If we look at 35 EUV systems in 2020, we still view that as a perfectly “doable” number and we should just pay attention to progress on that.

Supply chain is the biggest issue…
Of the things to be worried about is the supply chain. While ASML can manage its own manufacturing, supply of critical components from outside suppliers is less under control especially those parts that originate from all parts of the globe. Given the very specialized and advanced nature of the tools there are many components that are single sourced. Lenses are obviously the most critical example. Many components, such as lenses, have long lead times and “safety stock” which helps buffer near term disruptions but it is unclear how long the Covid impact will last and what permanent impact it could have on the supply chain. A longer term impact could use up the “safety stock” or WIP buffer

Long term demand not impacted…yet…
Second on our list of concerns is longer term demand. As we have pointed out in recent notes, we remain concerned about the demand for semiconductors in general and more specifically memory as the economic impact of Covid19 trickles down to consumer demand for electronics.

So far the company stated, and we agree, that customers have not canceled or pushed out orders as the lead times for tools are so long that no one wants to get out of line and risk future delays of a technology roadmap as litho tools are the critical gating item in increasing fab capacity or pushing Moore’s law forward.

Right now TSMC, Samsung and Intel remain in a race to move forward with Moore’s Law as quickly as possible. If anything this race has heated up as AMD is a bigger threat to Intel and Samsung wants to get business back from TSMC, while TSMC wants to maintain its lead.

Memory feels like its coming back but it is also most at risk to see orders slow of push out so we will try to keep a sharper eye on memory outlook. It would likely take a couple of quarters of Covid induced economic slow down to trickle down to chip makers, with memory fabs first to be impacted.

At this point we are in a bit of wait and see on future demand but in the mean time business remains solid and plans on track.

April 22, 2020September 30, 2020

Accelerating Edge Inference with Flex Logix’s InferX X1

Accelerating Edge Inference with Flex Logix’s InferX X1
by Mike Gianfagna on 04-22-2020 at 10:00 am
Categories: AI, eFPGA, Events, Flex Logix, IP

For a long time, memories were the primary technology driver for process development. If you built memories, you got access to cutting-edge process information. If you built other products, this could give you a competitive edge. In many cases, FPGAs are replacing memories as the driver for advanced processes. The technology access benefits still apply and at least one company, Flex Logix, is reaping those benefits.

Flex Logix has been known for their embedded FPGA technology, providing the best of both custom logic and programmable logic in one chip. On April 9, the company disclosed real-world AI interference benchmarks for its InferX X1 product. This new product contains both custom logic and embedded programmable logic.

An eye-popping overview of the benchmark results was presented at the Spring Linley Processor Conference on the same day. This popular conference was conducted as a virtual event. I got a chance to attend many of the sessions and I can say that The Linley Group did a great job capturing their live event in a virtual setting, delivering both high-quality presentations and providing informal access to the presenters. Expect to see more events like this.

The presentation was given by Vinay Mehta, AI inference technical marketing manager at Flex Logix. Prior to joining Flex Logix, Vinay spent two years at Lyft designing next generation hardware for Lyft’s self-driving systems. His activities included demonstration of quantization and hardware acceleration of neural networks and evaluation of edge and data center inference accelerator hardware and software. Vinay is a very credible speaker on AI topics.

Vinay’s presentation covered an overview of edge computing, customer requirements, characterizing workloads, a discussion of throughput vs. latency for streaming, benchmark details and convolution memory access pattern strategies. Here are some the highlights of Vinay’s talk…

The InferX X1 is completing final design checks and will tape out soon (TSMC 16FFC). It contains 4,000 MACs interconnected with Flex Logix’s EFLX eFPGA technology. This flexible interconnect helps the product achieve high utilization. Total power is 13.5 watts max, with typical power consumption substantially lower. Chip samples and a PCIe evaluation card are expected in Q3 2020. The part has flexibility built-in to support low-latency operation for both complex and simpler models at the edge.

Vinay covered many aspects of customer benchmarks for the InferX X1. To begin with, power and size stack up as shown in the figure below. The Flex Logix part appears to be lower power and less expensive (thanks to the small die size).

Regarding performance benchmarking, Vinay spent some time reviewing the various benchmarks (e.g., MobileNet, ResNet-50, Inception v4, YOLOv3). He also explained that many benchmarks assume perfectly ordered data, which often is not the case in real-world workloads. Putting this all together to examine benchmark performance for latency-sensitive edge applications yields the figure below. Note these results focus on latency without regard to power and cost.

Vinay pointed out that the view above isn’t holistic in the sense that customers will be interested in the combination of performance, power and cost. Looking at the benchmark data through the lens of throughput relative to die size, which is a proxy for cost, you get the figure below. The InferX X1 has a clear advantage thanks to its small size and efficient utilization of resources.

Vinay then spent some time explaining how various convolutional neural network (CNN) algorithms are mapped to the InferX X1 architecture. The ability to “re-wire” the part based on the memory access patterns of the particular convolutional kernel or series of convolutional kernels being implemented is a key reason for the results portrayed in the figure above. Flex Logix’s embedded FPGA technology provides this critical level of differentiation, as it allows for more complicated operations (such as 3D convolutions) to map efficiently to its unique 1D systolic architecture.

Vinay’s talk covered many more aspects of real-time inference requirements at the edge. There was also a very useful Q&A session. If you weren’t able to attend his presentation at the Linley Conference, there is a replay available. I highly recommend you catch that. You can register to access the replay here. The presentation is on day four, April 9, 2020 at 11:10 AM.

April 22, 2020April 15, 2022

How does TensorFlow Lite on Tensilica HiFi DSP IP Sound?

How does TensorFlow Lite on Tensilica HiFi DSP IP Sound?
by Tom Simon on 04-22-2020 at 6:00 am
Categories: AI, Cadence, IP

In all the hubbub about AI/ML, it’s easy to see why visual ML gets more attention. It’s got appeal because of applications such as autonomous driving. Because of this it’s easy to overlook the importance of audio ML. I own a Tesla and putting it into autopilot is very cool, but even it has voice recognition built in as an important feature to reduce driver distraction. At home I have numerous Google Minis that we use every day for controlling our heating, lights, etc. When all is said and done I am sure I use our voice ML appliances more often than the Tesla Autopilot.

Audio ML is most useful when it runs on the edge, not in the cloud. This enhances security because the audio stream does not need to travel to the cloud. Local ML processing also improves latency and lowers network loading. With this in mind, Cadence just announced support for TensorFlow on their Tensilica HiFi DSPs. Along with the announcement on their website, Cadence also gave a presentation, titled “Efficient Machine Learning on HiFi DSPs Using TensorFlow”, at the Linley Processor Conference in March. This year, of course, the conference was held online due to Covid-19.

Yipeng Liu, Technical Marketing Director at Cadence for Tensilica IP, started off the talk with a discussion of how audio ML was recently found useful in China to help prevent the spread of the Covid-19 virus. Once elevator buttons were found to be a transmission risk, a team of engineers rapidly developed a voice activated system that worked in the acoustically difficult elevator environment to let riders control the elevator.

Embedded edge devices present several constraints for deploying ML, including small memory sizes and limited processing capabilities, both of which can lead to difficulties in coding effective solutions in a timely manner. There are optimization methods that can be employed; however, they make the process more manual and ad-hoc. Edge-based hardware usually has fixed-point math units and also requires C/C++ rather than Python code.

Cadence is offering TensorFlow Lite for Microcontrollers (TFLM) targeted at its Tensilica HiFi DSP IP, which effectively deals with these limitations. Included in TFLM is the HiFi Neural Network library (NN lib), HiFi Nature DSP library (NDSP lib) and 8/16/32 bit SIMD and VFPU support. The libraries are optimized for all Tensilica HiFi DSPs. The libraries are also framework agnostic.

Yipeng also talked about the Tensilica XAF middleware that allows for faster system integration. It handles memory allocation and management. It also has the ability to install and uninstall components to save memory. Yipeng said that XAF middleware simplifies integration of ML and also traditional audio components from multiple providers.

We live in a world where audio information plays a huge role. Even though image processing gets the limelight, audio processing enables many important tasks. These range from voice processing, to song recognition, and a host of other important tasks. Now with the ability to easily add ML to devices at the edge, the applications and uses for this technology will expand further. Cadence is now providing a way to develop and deploy these applications with much less effort with the widely used TensorFlow platform. Full information about Cadence TensorFlow Lite for Microcontrollers can be found on the Cadence website.

Also Read:

Ultra-Short Reach PHY IP Optimized for Advanced Packaging Technology

Cadence Dives Deeper at Linley Fall Processor Conference

Leveraging Virtual Platforms to Shift-Left Software Development and System Verification

April 21, 2020April 15, 2022

The Quiet Giant in Verification IP and More

The Quiet Giant in Verification IP and More
by Mike Gianfagna on 04-21-2020 at 10:00 am
Categories: IP, SmartDV

In the technology industry, we’re all used to the hype about the latest and greatest. Semiconductor IP participates in the over-drive news cycle from time to time as well. So, when I see a company that has real, solid credentials but has resisted the temptation to over-hype, it gets my attention. I had an experience like this recently relative to SmartDV.

The company is a new sponsor for SemiWiki, and I spent some time recently speaking with Barry Lazow, their vice president of worldwide sales and marketing. Barry has been doing high technology sales work for quite a while, all the way back to VLSI Technology, arguably one of the true pioneering companies in semiconductor. I took the opportunity to probe Barry about the story behind SmartDV.

What I found was, in a word, breathtaking. First of all, the company is self-funded. No VC commitments, no need to waiver from their core focus, which is stated as “being #1 in verification and design IP,” a lofty goal. Barry describes the company as a family business, with the founding team of chip design and verification experts still in place after 12 years. The company’s development team of over 250 people is located in Bangalore, India.

They maintain a three-shift operation there to ensure worldwide coverage for customer support, which they earn high marks for from their customers. Doing centralized support this way can be challenging and it seems SmartDV has figured out how to do it right. Speaking of customers, Barry explained that more than 100 companies worldwide rely on SmartDV’s products, including seven of the top ten worldwide semiconductor companies.

So, what does SmartDV offer? Their focus is on verification IP (VIP) and design IP, with over 400 titles in their portfolio. The figure below drives home the point about being #1.

In the VIP area, the SmartDV portfolio is quite robust. It includes models for simulation, emulation (synthesizable transactors (SimXL) for accelerating emulation), assertion-based VIP (formal verification), FPGA prototyping and verification (with a supplied LINUX Perl driver), post-silicon verification and a visual debugger called SmartViP debug for rapid analysis of protocol issues. Probing a bit more, SmartDV’s VIP has native support for UVM, System Verilog, VMM, OVM, Vera, Verilog and SystemC/TLM. Quite a list. Each VIP also includes a compliance test suite and a functional coverage model, which is not always the case with VIP.

Barry pointed out another key attribute of this VIP, the ability to seamlessly transition from simulation to emulation. I have plenty of stories of that transition taking many months. I recall the term “design for emulation”. You probably have some of your own stories. An easy transition to emulation is a big deal. All the major emulators are supported of course. Another statistic Barry shared was from his customers, who report compile times for SmartDV VIP being 2-3X faster than the competition. Impressive.

In the design IP area, SmartDV offers synthesizable RTL in Verilog or VHDL to cover popular interfaces such as MIPI, AMBA, PCI, CAN, RapidIO and so on. After our tour of IP products, just when I thought I had heard all the juicy stuff, Barry gave me one more tidbit – perhaps the key secret of SmartDV’s success. SmartDV’s products are typically sold as soft, compilable IP. Nothing really new there. What is new is that ALL of their products are built with a proprietary compiler technology which utilizes a proprietary language that drives the process.

This has some significant implications. Let’s start with the myth of standard, off-the-shelf IP. We all know that does happen sometimes, but often there are tweaks needed to use an IP block effectively. That usually translates into additional manpower at the vendor to implement the tweaks and associated delivery delays. This is not the case at SmartDV. Thanks to their proprietary compiler, the company can implement modifications in days. This is one of the reasons for their high marks in customer support. Barry explained that an entirely new piece of VIP can typically be done in 4-6 weeks, but typical customization is done in 1-2 weeks. This allows the company to be first to market supporting virtually all new and emerging protocols, as depicted in the figure below. As an example, SmartDV was first to market with VIP to support TileLink, the RISC-V interconnect fabric.

SmartDV also provides verification services – they are a one-stop shop for a huge part of a project’s verification needs You can learn more about this quiet, but potent company at the SmartDV website. If you have verification or design IP needs for your next project, I strongly recommend you start there.

Also Read:

SemiWiki and SmartDV on Verification IP

Secret Sauce of SmartDV and its CEO’s Vision

SmartDV at DAC and More

April 21, 2020April 14, 2022

That Last Level Cache is Pretty Important

That Last Level Cache is Pretty Important
by Bernard Murphy on 04-21-2020 at 6:00 am
Categories: Arteris, IP
1 Comment

Last-level cache seemed to me like one of those, yeah I get it, but sort of obscure technical corners that only uber-geek cache specialists would care about. Then I stumbled on an AnandTech review on the iPhone 11 Pro and Max and started to understand that this contributes to more than just engineering satisfaction.

Caching

A brief refresh on caching. This is a method used in processors and in more general SoCs to minimize the need to go off-chip to read or write memory. Off-chip accesses are slow and burn a lot of power. If you already have the data around in on-chip memory – a cache – you should read or write that memory instead. This is a frequency-of-access play. You can’t get rid of the off-chip memory, but you can reduce the number of times you have to go there, speeding up net performance and reducing net power consumption.

It’s common to have a hierarchy of caches. These start with small caches really close to a CPU or IP for very fast access, then bigger caches a bit further away (but still on chip) to serve a bigger demand though not quite as fast.

The last level provides caching for the whole chip, bigger still, a little slower still and the last line of defense before you have to go to main memory.

In a modern SoC with CPUs and GPUs and AI accelerators and who knows what else, this cache has to serve a lot of different masters. Which is important because how effectively a cache does its job is very dependent on the application, extra tricky when the last level cache has to serve a bunch of different applications.

Pointer-chasing

There are a number of pointer-based programming data structures, especially popular in data analytics and machine learning kernels, which can particularly stress caching. These include linked-lists, trees and graphs. In all these cases to trace through a structure you have to chase through pointers to work through a list or a path through a tree or graph. Because this is pointer-based data there’s no guarantee it will all fall close together in memory, which makes it harder to get all of it into a cache limited to caching some fixed number of memory blocks. Chasing through those pointers is most likely to stress the ability of a cache to keep the relevant data local without needing to go out to main memory.

The iPhone 11 review (more exactly the Apple 13 Thunder SoC review)

So AnandTech ran a pretty detailed set of pointer-chasing tests on the A13 and compared these with results for the A12 Tempest (and variously some other phones in some graphs). In most of the charts they compare latency (speed of access) versus test depth (how many pointers are chased).

They show a latency versus test depth curve for A12 and A13 with identical or improved latencies in the first and second level caches but consistently better latency in the last level cache (which they call the system level cache – SLC). In the upper right of the graph, A13 is slower than A12 but that’s for off-chip memory accesses. SLC access are one level below and left of those.

AnandTech concludes that Apple is very effectively using that last level cache to get better overall system performance. And they note later that the A13 SLC maintains bandwidth versus test depth much better than in the A12. All adding up to better system performance across many applications. If it’s that important to Apple, I’d have to guess is should be just as important to everyone else.

Arteris IP CodaCache

Caching and interconnect are very tightly tied together. When multiple IPs each have their own local caches, those must be kept coherent. When an attempt to find a piece of memory in a local cache fails (a cache miss), the request must be passed onto the next level and so on until if the last level cache can’t help, it has to go out to main memory. A big drag on latency and power in those cases.

Arteris has built a general-purpose highly-configurable last level cache, their CodaCache, for such applications. They’ve had this for a little while. What’s new about this implementation is that it now meets ISO 26262 functional safety compliance, in line with Arteris IP general directions in safety. You can learn more about CodaCache HERE.

Also Read:

Trends in AI and Safety for Cars

Autonomous Driving Still Terra Incognita

Evolving Landscape of Self-Driving Safety Standards

April 20, 2020April 26, 2022

SPIE 2020 – ASML EUV and Inspection Update

SPIE 2020 – ASML EUV and Inspection Update
by Scotten Jones on 04-20-2020 at 10:00 am
Categories: Lithography, Semiconductor Services, TechInsights
1 Comment

0.33 NA EUV systems for HVM Ron Schuurhuis Page 02

I couldn’t attend the SPIE Advanced Lithography Conference this year for personal reasons, but last week Mike Lercel of ASML was nice enough to walk me through the major ASML presentations from the conference.

Introduction
In late 2018, Samsung and TSMC introduced 7nm foundry logic processes with 5 to 7 EUV layers, throughout 2019 both companies ramped up those processes and they are currently in high volume production. This year Samsung and TSMC are both ramping up 5nm foundry logic processes with 12 to 14 EUV layers and Intel is working on their EUV based 7nm process expected next year. Intel’s 7nm process should have densities comparable to Samsung and TSMC’s 5nm processes.

Samsung has also introduced their 1z DRAM process in late 2019 that initially was optical but then transitioned to a single EUV layer. In late March 2020 Samsung announced they had shipped one million DRAM modules with EUV based DRAMs. Samsung’s next generation DRAM process, the so called 1c generation DRAM is expected to have 4 EUV layers.

Clearly EUV is now accepted as best solution for critical layers for leading edge logic and DRAM production.

Mike discussed four presentations with me:

Current production is being done with 0.33NA systems and ASML presented a current status and roadmap for these systems.
The EUV source is a key component of the systems and the details of a new improved source were described.
The status of efforts to produce a 0.5NA system improving resolution and productivity.
ASML bought HMI and is continuing to develop their multi beam – Ebeam wafer inspection technology.

0.33NA Systems
The promise of EUV is summarized in figure 1.

Figure 1. Why ASML customers want EUV.

By the end of 2019 ASML had shipped 53 systems and over 10 million wafers had been exposed in the field. Figure 2 presents the systems shipped and wafers exposed by quarter.

Figure 2. EUV systems shipped and wafer exposed.

One particularly impressive aspects of figure 2 is the background photo that shows rows of EUV systems installed at an undisclosed customer site.

The current systems in the field are the NXE:3400B that have now demonstrated an average of >1,900 wafers per day (wpd) for one week, and >2,700 wpd for the best day.

Figure 3 illustrates that average availability is now reaching 85% with the top 10% of systems at 90%. 90% has long been the goal for the 3400B systems and ASML continues to work to tighten the 3400B system availability around 90%.

Figure 3. NXE:3400B availability trend.

ASML has now started to ship the NXE:3400C, the next generation system. The NXE:3400C features improved optics and mechanical throughput achieving an approximately 20% increase in throughput over the 3500B at 160 wafers per hour (wph) at a 20mJ/cm² dose and 135 wph at a 30mJ/cm² dose. The 3400B was always specified at a 20mJ/cm² dose for throughput, the 30mJ/cm² is in recognition of the need to increase dose as the feature sizes shrink. Authors note, I believe that even for 7nm foundry logic, the current doses are higher than 30mJ/cm².

The 3600C features several improvements to the system to increase availability and the target is to reach 95%, the same availability that is achieved with DUV systems. The improvements will be discussed further in the paper on the source.

In mid-2021 ASML expects to ship the NXE:3600D with 160 wph throughput at a 30mJ/cm2 dose and longer terms there are plans to introduce a system with >=220 wph at a 30mJ/cm² dose. The key to continual improvements in throughput are higher source power (see the EUV source section) and faster mechanical handling.

These throughput improvements are achieved while continually improving dose accuracy, overlay, CD uniformity and focus uniformity.

Figure 4. 0.33NA system roadmap.

EUV source
The largest availability loss causes on the 3400B system are the droplet generator and collector mirror, see figure 5.

Figure 5. Causes of availability loss.

The 3400C system directly addresses these issues with automated refills of the tin generator and a fast swap droplet nozzle and an easy access door for fast collector mirror swaps.

Figure 6. NXE:3400C availability improvements.

The lifetime of the collector mirror is also continuously improving while the power is also increasing.

Figure 7. Collector lifetime.

The net result of these improvements is a target for 95% uptime for the 3400C system in the field.

Looking forward at continued improvements in throughput ASML continues to drive up source power. Figure 8 illustrates the trend in source power. Note that the lag from research to high volume manufacturing is approximately 2 years so that we could possibly see a 500-watt source (the current source runs around 250-watts) around 2022.

Figure 8. Source power trend.

0.5NA System
The resolution of an exposure system is inversely proportional to NA. As critical dimensions shrink 0.33NA EUV systems will require multi-patterning to print the smallest features. The goal with the high NA systems is to match overlay and productivity of 0.33NA systems while enabling single pass lithography to be extended to smaller features.

The optical system for the 0.5NA systems is anamorphic, that is the magnification 4x in one direction and 8y in the orthogonal direction. This result in the field size being ½ of what it is for a 4x/4y system with the same reticle size. In order to achieve the high productivity goals the acceleration of the mask stage is 4x of a 0.33NA system and the acceleration of the wafer stage is 2x of a 0.33NA system.

Figure 9. 0.55NA system anamorphic lens.

Improvements in transmission in the fast stages result in improved throughput over the 0.33NA system at the same throughput. It should be noted here that some of the high speed sateg technology developed for the 0.55NA systems are being implemented on the 0.33NA systems to further improve throughput on those systems as well.

Figure 10. 0.55NA system throughput advantage.

Currently ASML is realizing the wafer and mask stage acceleration and finalizing the architecture. The main differences from the 0.33NA systems are the new optics system and faster stages although once again the faster stage technology is being used for the 0.33NA systems.

The 0.55NA systems also require better alignment and leveling. ASML is currently testing specific configuration to determine particle generation at high acceleration and are starting to gather some of the first sensor data.

ASML is also building out the infrastructure for the 0.55NA systems at various facilities around the world.

ASML Wilton Connecticut is responsible for the reticle stages.
At ASML headquarters in Veldhoven in the Netherlands the systems will be assembled.
Ziess in Oberkochen Germany is responsible for the optics fabrication.
ASML San Diego California is responsible for the source.

4 systems are currently on order with systems expected to be available in the 2022/2023 time frame.

Multibeam EBeam
ASML acquired HMI and has continued to pursue the HMI multibeam EBeam exposure technology. Ebeam inspection has very high resolution but is very slow taking approximately 2 hours to inspect 0.1% of a wafer.

The multibeam approach utilizes 9 beams in a 3 x 3 array all scanning simultaneously. Figure 11 illustrates the basic tool concept.

Figure 11. Multibeam EBeam system concept.

ASML has now demonstrated <2% cross talk between the beams and they are applying stage technology from their DUV exposure tools to improve the multibeam system throughput. They are targeting a 5-6x improvement in throughput and longer term are working on a 25-beam system.

Conclusion
EUV is now the solution of choice for critical lithography for leading edge processes. ASML continues to show progress both in the current 0.33NA generation systems and the development of next generation 0.55NA systems.

Also Read:

SPIE 2020 – Applied Materials Material-Enabled Patterning

LithoVision – Economics in the 3D Era

IEDM 2019 – Imec Interviews

April 20, 2020April 26, 2022

Design IP Revenue Grew 5.2% in 2019, Good News in Declining Semi Market

Design IP Revenue Grew 5.2% in 2019, Good News in Declining Semi Market
by Eric Esteve on 04-20-2020 at 6:00 am
Categories: IP, IPnest, Semiconductor Services

Good news is good to hear, particularly these days! The behavior of the Design IP market in 2019 is extremely positive, when the semiconductor market has seen a decline worst than in 2009 (economy crisis) or 2001 (internet bubble collapse). Analysis this 5.2% growth in detail will help to understand the future of the IP market, as we think this market exit a decade based on smartphone explosion fueling the IP growth, to enter in the 2020 decade we expect to be data centric. But let’s have a look at the main trends shaking the Design IP in 2019.

ARM is still a solid #1, with more than 40% market share… but ARM is staying flat year over year. If we dig, we find that ARM license revenues have grown by 13.8% when royalty revenues have declined by 6%. ARM assign this lose in royalty to the smartphone volume decline and it make sense, considering ARM penetration in CPU and GPU IP in wireless phone.

The question that you may ask is about the impact of RISC-V on ARM revenues. The answer is that RISC-V adoption has certainly grown in 2019, but that it’s too early to measure the precise impact. This should clarify, but it will probably take a couple of years before we can measure the RISC-V penetration in term of revenues flow. Clearly the change on CPU IP business model is on-going, and customers are happy to support this evolution!

Now, let’s have a look at the various IP vendors who have been successful, as well as IP categories growing share of the IP market.

Synopsys and Cadence, respectively #2 and #3, are growing respectively by 13.8% and 22.9%. Synopsys highest growth come from the Interface IP category (19.3%), the other categories also contributing, but less, when Cadence growth is shared between Interface IP (thanks to Nusemi acquisition, but not only) and DSP IP (Tensilica).

Both EDA vendors are positioned as “one-stop-shop” IP suppliers, both have created their IP offer by running the acquisition of small to mid size vendors leaders on their segment. Synopsys has started in the early 2000’s when Cadence positioning in IP has started with Denali acquisition in 2010.

This growth rate is the clear signal showing that their IP long term strategy is successful. Being a “one-stop-shop” supplier strategy has been made possible because both were large enough companies with deep pocket allowing the multiple acquisitions to make to support this positioning.

We will see that the other winners in the IP market are, at the opposite, companies being extremely focused and able to be technical leaders on their segment or sub-segment.

Lesson to learn from the IP category evolution between 2018 and 2019. In processor we aggregate CPU, DSP and GPU IP categories. Interface is one category, integrating the protocol-based function like USB, PCI Express, Ethernet, MIPI, SATA, DP, but also Die-to-Die (D2D) interface and memory controller (DDRn, LPDDRn, HBM, GDDR).

We can see that the market share of processor has moved from 53.5% to 51%, when interface category has enjoyed, passing from 20.3% to 22.1%. To make sure that this is a real trend and not an artefact, I have checked the status is 2016. Processor was weighting 63.8% when Interface was only 16.9%.

The remaining two groups are “Other Physical”, aggregating various categories, “SRAM memory compiler”, “other memory compiler”, “physical library”, “Analog & Mixed-Signal” and “Wireless Interface” and the last group is “Other Digital”. Both groups are relatively stable, which means that they have grown at the same rate that the rest of the IP market, a bit more with “other physical” moving from 18% to 18.8%.

The interface IP market is the big winner in term of growth and market share, weighting $870 million in 2019. It’s not a surprise for IPnest, who will deliver the 12th version of the “Interface IP Survey & Forecast” in June 2020!

In 2009 Interface IP category was weighting $220 million, it has been multiplied by 4X in 10 years!

If we think in term of application or market segment, the evolution of interface IP is illustrating the move from wireless phone to data centric. In 2010, a large part of interface IP business was generated by smartphone SoC integrating protocols like USB, memory controller, HDMI, DP, SATA and MIPI, but no PCIe or Ethernet.

In 2019, we think the data-centric applications represent the largest share of interface IP business. Data-centric like data center, server, wired networking and 4G/5G base stations. In all these applications you can find advanced memory controller (DDR4, HBM2, GDDR6), PCIe and Ethernet requiring high-speed SerDes (up to 56G if not 112G) and emerging die-to-die (D2D) solutions.

Smartphones will obviously continue to integrate USB, HDMI or LPDDRx memory controller, but we expect the growth of IP market to be generated by data centric application during the 2020 decade.

If we need an example to illustrate this trend, let’s take the GPU IP usage in smartphone. The two market leaders, Samsung and Apple, have changed from GPU IP supplier (ARM or IMG) to a non-IP vendor. Apple has decided to develop GPU internally and Samsung has closed a deal with AMD to use their GPU.

On the other hand, IPnest think about creating a new sub-category in the Interface IP, to be specific related to Die-to-Die (D2D) interconnects. D2D protocols are in discussion, it can be based on massive parallel interface or high-speed SerDes (40G to 112G) and chips are already in production from AMD or Intel. We can expect D2D adoption to generate good business in the mid-term as chiplet can be a good work around for Moore’s law limitation…

To come back to the IP market successful companies, as already mentioned, they can be ranked in two groups. Large EDA companies offering a one-stop-shop IP portfolio, Cadence and Synopsys, and very focused vendors, leader on one (or very few) product.

Let’s mention a few examples.
– Arteris IP with the Network-on-Chip (NoC), who has made 60% YoY growth, joining the Top 15 with revenues above $30 million in 2019.

– Silicon Creations, leader of the Analog Mixed-Signal (AMS) category in 2019 and 2018, the company being about ten years old and now #1 before Synopsys.

– Alphawave has been created in 2017 by a serial entrepreneur, Tony Pialis, being part of the Snowbush starting team, creating Vsemiconductor, acquired by Intel. Alphawave now enjoy $25 million revenues in 2019, based on advanced SerDes, after just two years !

– SST offering NVM IP, undisputed leader of the category, with revenues passing $100 million or more than two times the #2 revenues.

What is the secret for these IP vendors? Quality of the design (and product) is certainly the #1, being able to offer an innovative and advanced solution come right after. I should come back on these success stories, as each of them is like a novel, you want to turn the page!

FYI, IPnest will deliver in June 2020 the “Interface IP Survey 2015-2019 – Forecast 2020-2024”, as every year since 2009.

Eric Esteve from IPnest

To buy this report, or just discuss about IP, contact Eric Esteve
(eric.esteve@ip-nest.com)

Also Read:

Chiplet: Are You Ready For Next Semiconductor Revolution?

IPnest Forecast Interface IP Category Growth to $2.5B in 2025

Design IP Sales Grew 16.7% in 2020, Best Growth Rate Ever!

April 19, 2020July 6, 2020

Short vs Long Term Covid19 Impact

Short vs Long Term Covid19 Impact
by Robert Maire on 04-19-2020 at 10:00 am
Categories: Semiconductor Advisors, Semiconductor Services

-Short term Covid19 impact is primarily logistics related
-Longer term impact is more systemic/demand driven
-Impact will wind through supply chain over several qtrs
-Other issues, such as trade, remain an overhang

Short term versus long term in the semiconductor industry
The stocks declines over the last months seem to indicate the semiconductor industry flying off a cliff without leaving any skid marks behind. Reality may not be quite as bad as other industries such as airlines, restaurants, hotels etc; as the semiconductor industry is by nature a longer term, slower moving, inherently cyclical animal.

The food chain in semiconductors is fairly long as it can take months to produce chips and the entire life cycle from design to production is usually well over a year. There is a lot of inventory and buffer in the supply chain and unlike the food industry, nothing has a short shelf life.

Airline seats, hotel rooms and food all have a very definitive shelf life which goes to zero value on expiration.

The semiconductor industry doesn’t instantly react to short term changes in demand as those near term changes are absorbed by the supply chain buffer. There is an added “shock absorber” of pricing, which rises and falls depending upon demand and inventory levels.

The semiconductor equipment industry is even more long term in nature, than the chips themselves, as new fabs and fab expansions can take years to plan and even just rolling in one piece of equipment can take several quarters from order to install.

This suggests the semiconductor industry as a whole has the momentum a a very large oil tanker that takes a very long time to either accelerate or stop.

Near term Covid19 issues are primarily logistics
The primary Covid19 impact to the semiconductor industry in Q1 2020 is due to logistical issues of moving people and materials around.

In general, the fabs kept operating for the most part. Fabs tightened down on access by outside persons to the fabs for fear of infection. Tool shipment and installs were slowed due to transport and access issues.

Tool manufacture was impacted by supply chain issues (moving sub components around) as well as people.

The semiconductor manufacturing base relies on free, easy and quick movement of materials and people around the globe and was obviously impacted when that slowed.

To be very clear, we have not heard of any major change in fab plans, expansions, upgrades, and technology advancement that has been impacted in a big way so far. Its not like a foundry is going to cancel its next gen process or significantly delay it.

There have been reports of Samsung delaying its 3NM from 2021 to 2022 and blaming Covid19. While its clear that Covid19 is causing one to two quarter delays in equipment installs and EUV tools were cited as one issue, we think that Samsung has historically been more than overly optimistic in its projections in beating TSMC to the next gen. Samsung has missed most of its prior projections of technology readiness.

When all is said and done we expect a one to two quarter overall delay or “hiccup” in the march of Moore’s law, caused by primarily logistics issues related to Covid19.

Longer term, demand driven issues, harder to determine

We think the bigger variable, and one that is harder to project, is demand driven issues caused by Covid19.

One of the reason’s why this is difficult is that we are still at the very beginning of economic impact with wildly varying estimates of economic damage and impact.

In general, semiconductor laden devices are “less essential” goods than food, shelter, transport & energy (though some may argue they need their smart phone more than food…).

While there may be a near term spike in demand for laptops and servers due to remote work and learning, we are more concerned about reduced demand for TVs, cars, smart phones, 5G etc; as those purchases tend to be more “marginal” and vulnerable to high unemployment or business cutback in spending.

Slowing of semiconductor demand will only be felt over the next several quarters and not felt in Q1 as we haven’t yet seen significant demand driven issues and we have the above described supply chain buffer to delay the impact.

We remain very concerned about the precarious balance of supply and demand in the commodity like memory markets and would watch those with extreme interest. We have already seen some warning signs in memory pricing.

We also remain concerned about the iPhone 12 launch in the fall, which has always been timed for holiday purchases. Getting pushed out by a quarter would essentially miss the holiday window of sales.

We would look to the 2008/2009 financial crisis as a bit of a guide for potential impact on semiconductors, which was significant.

Except for the recent, self inflicted, memory oversupply driven down cycle, the semiconductor industry has been in a positive overall trend since 2008/2009. If we hadn’t over built memory supply, we would likely have still been in the longest up cycle ever.

This most recent down cycle lasted about a year and a half and most prior cycles lasted two years or more.

While the short term, logistics driven impact may only last one or two quarters at most, the longer term, demand/economic driven impact will likely last one to two years.

Right now the depth of the impact cannot be determined but its safe to say that the long term impact will last at least as long as the overall economic impact.

Samsung, Intel & TSMC still spending for now
We continue to hear positive things about spend levels. In fact it sounds like Samsung may be planning on ramping spending in a similar fashion as they did in the prior upturn.

We have also heard that Intel continues to spend to get capacity it has been short of as well as take advantage of near term spikes in demand.
TSMC also continues its roll out of new technology and is remaining on track with prior plans for the most part.

The bottom line is that so far, no major player in the semiconductor industry has taken their foot off the gas (for now).

Between Apple, AMD, Intel, Qualcomm & Huawei among others, TSMC seems to have more than enough demand to keep it busy. Our concern here is that TSMC has broad exposure across the consumer industry and obviously more exposure to 5G roll out which could be impacted.

Samsung is obviously very exposed to memory pricing but in the past has spent up and until memory prices collapsed in their face, then put the brakes on instantly. Samsung behaves in a much more binary way as it seems to be either full on the gas or full on the brakes with not a lot in between.

Intel seems to be a more consistent spender, and if anything, likely too conservative as evidenced by delays and shortages of parts. Of the big three, we think Intel is least at risk to change their capital spending plans and perhaps more at risk for an up tick in spend.

Early Q1 signals mixed- ASML & ACLS
Early signals coming out of the equipment industry are mixed. On one hand we have heard that ASML will miss expectations due to logistics issues of shipping and installing tools which is totally expected and obviously beyond their control. On the other hand we have just heard this morning that Axcelis will exceed the high end of guidance with a great quarter despite Covid19. Obviously shipping and installing scanners is much different from ion implanters and the customer base and locations are significantly different between the two companies.

We think that impact on tool companies will vary depending upon customer locations and complications associated with tools. We think that Axcelis is one of the few companies that will see relatively no impact. Most will see some sort of impact.

In general, materials suppliers remain a defensive bet as they will likely have the shortest term impact related only to any fab slow downs which are few.

Those companies with the widest and longest supply chains that are most exposed to logistics will see the most impact, especially those with more Asia based manufacturing.

The Stocks….Beware the bounce…..
The stocks have bounced off a sharp decline as worst case fears seem to have abated. Initial reports are coming in better than expected and we expect will continue to come in better than worst fears.

We also expect that guidance for Q2 will probably also be better than expected as much of the business pushed out of Q1 will wind up in Q2 so it will make up for any weakness and potentially look better than originally expected for many companies.

As we have pointed out here, we think near term issues are primarily logistics based and by their nature, short term. As such, the stocks will discount these issues as one time, delays in an otherwise intact model. When we add the likely positive Q2 guide the stocks should see a short term “pop”

We are more concerned about business one to two or more quarters out, driven by demand issues.

So while we have experienced a near term “dead cat bounce” off a low bottom we are concerned that the stocks could drift down in the longer run after having a “relief rally” when investors realize that short term impact is just that.

We also remain very concerned about non Covid19 issues, such as Huawei/China trade, which has all but been forgotten about by investors. The current administration could look to China as a scapegoat for Covid19 and try to punish China through Huawei or some other trade impacting mechanism.

In short we may try to take advantage of a short term, quarter driven pop in the stocks but then take some money off the table as the future looks a bit more uncertain post the pop of the quarter.

April 19, 2020April 25, 2020

Wave Computing and MIPS Wave Goodbye

Wave Computing and MIPS Wave Goodbye
by Mike Gianfagna on 04-19-2020 at 8:00 am
Categories: AI, IP
6 Comments

Word on the virtual street is that Wave Computing is closing down. The company has reportedly let all employees go and will file for Chapter 11. As one of the many promising new companies in the field of AI, Wave Computing was founded in 2008 with the mission “to revolutionize deep learning with real-time AI solutions that scale from the edge to the datacenter.” Classified as a late stage venture, the company was founded by Dado Banatao and Pete Foley. Mr. Banatao serves as chairman of Wave Computing and is also a managing partner at Tallwood Venture Capital. Sanjai Kohli is the current CEO. Mr Kohli took the helm at Wave Computing in September 2019 from Art Swift, who held the position for only four months. The story was reported in EE Times here.

The story speculated that there were performance issues with Wave’s AI dataflow processor. Did that contribute to their early exit? At present, the reasons for their exit are speculative. Wave Computing offered a broad product line. Billed as a “scalable, unified, AI platform,” Wave Computing utilized MIPS processors to offer dataflow processing technology that scaled “from the edge to the datacenter.”

To make things more interesting, MIPS Technologies is owned by Wave Computing, who acquired it from Tallwood MIPS Inc., a company indirectly owned by Tallwood Venture Capital. What now happens to MIPS?

In December of 2018 Wave announced the MIPS Open Initiative to expand adoption of MIPS via open (free) licensing only to close it one year later:

“Wave Computing, Inc. and its subsidiaries (‘Wave’) regretfully announce the closing of the MIPS Open Initiative (‘MIPS Open’), and hereby give Notice of the same effective November 14, 2019 (‘Effective Date’),” the company’s brief email to registered MIPS Open users reads. “Effective immediately, Wave will no longer be offering free downloads of MIPS Open components, including the MIPS architecture, cores, tools, IDE, simulators, FPGA packages, and/or any software code or computer hardware related thereto, licensed under any of the (i) MIPS Open Architecture License Agreement (ver. 1.0), (ii) MIPS Open Core License Agreement ver. 1.0 For the microAptiv UC Core, (iii) MIPS Open Core License Agreement ver. 1.0 For the microAptiv UP Core, and/or (iv) MIPS Open FPGA License Agreement ver. 1.0 (collectively, ‘MIPS Open Components’. In addition, all MIPS Open accounts will be closed as of the Effective Date.”

Was Wave trying to do too much at once? Is narrower focus a better strategy in the emerging AI market? Again, speculation that will likely be brought into focus in the coming days and weeks. Did the current pandemic play a role? I believe those stories are yet to be told, it is likely too early for that.

The AI and deep learning market is exploding with many new companies offering novel approaches. Any new market typically experiences this growth, followed by a consolidation phase. Does the news from Wave Computing signal we are already entering the consolidation phase? Time will tell.

About Wave Computing
Wave Computing, Inc. is revolutionizing artificial intelligence (AI) with its dataflow-based solutions. The company’s vision is to bring deep learning to customers’ data wherever it may be—from the datacenter to the edge—helping accelerate time-to-insight. Wave Computing is powering the next generation of AI by combining its dataflow architecture with its MIPS embedded RISC multithreaded CPU cores and IP. More information about Wave Computing can be found at https://wavecomp.ai.