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Analog Sensing Now Essential for Boosting SOC Performance

Analog Sensing Now Essential for Boosting SOC Performance
by Tom Simon on 06-03-2021 at 6:00 am

analog sensing

In today’s System-on-Chip (SOC), analog blocks are used in many places such as I/O cells for communication, PLLs for generating clocks, LDO’s for converting supply voltage to internal rail voltage, Sensors for qualifying external characteristics such as temperature, light, motion, etc. However new advanced designs now require analog sensing circuits that are turned inward to monitor their own health and operation. Analog sensing is now needed for monitoring circuit temperature, voltages, process variation and other operational aspects.

Mahesh Tirupattur from Analog Bits recently gave a presentation, which is available for viewing on demand, that talks about the challenges SOC designers face in dealing with large die sizes, power supply issues, process variation and more. The presentation titled “Sensing the Unknown: Modern Method to Designing Chips” reviews a large chip case study and how sensing made its operation possible. Analog Bits has been designing on-chip sensors for many years and has expanded their capabilities to address issues encountered in the most advanced designs.

Chip designers have to thread the needle with every chip to gain maximum performance, area and efficiency while dealing with PVT variation and power supply issues. This is nearly impossible to do now without the ability to dynamically adjust operation to compensate for these factors. Mahesh discusses how Cerebras used glitch detectors from Analog Bits to provide real-time information on the power supply health in their massive AI processor. This AI engine measures 215 x 215 mm and has 1.2 trillion transistors. With 400,000 cores spread over a large die, local phenomenon could easily occur that can cause disruption.

Analog Sensing for SOC performance

The solution, according to Mahesh, was the addition of 840 distributed glitch detectors. They are provided as a fully integrated analog macro with a digital interface. The glitch detectors are user programmable, so the trigger voltages, depth of glitch and glitch time span can be set as per the needs of the specific design. Using the data provided, instantaneous current spikes can be suppressed.

Analog Bits started early with innovation in their PVT sensors. They are extremely accurate and operate with low power and a small form factor. It later developed power-on reset sensors to ensure the stability of supply lines in the core and IOs. These can also assist with brown-out prevention. The conpany’s most recent product family includes the power supply glitch detectors mentioned above. These can be abutted and have their own integrated voltage reference.

Analog Bits is also addressing SOC clocking issues. Once again without feedback and dynamic operation, clocks can be difficult to manage across large designs. Mahesh talks about their “Package Pin-less” technology that frees PLLs from pin requirements and allows more flexible placement on the die. This will enormously reduce clock power distribution, save bill of materials eliminating filter components and reduce test times.

Analog bits has developed their analog IP for process nodes from 0.25 microns down to the most advanced FinFET processes, such as 12nm, 7nm, 5nm and 3nm at fabs such as GLOBALFOUNDRIES, Samsung and TSMC. In all they support over 200 process nodes. Because they develop a broad line of analog macros, they share common functional units to ensure higher quality and interoperability. Importantly, to make their business model easier for their customers, they do not use a royalty model.

The presentation, which is part of this year’s Simulation World event, provides good insight into Analog Bits and their offerings. If you want to view the video of the presentation it can be found at the Simulation World website.

Also Read:

Analog Bits is Taking the Virtual Holiday Party up a Notch or Two

Analog Bits is Supplying Analog Foundation IP on the Industry’s Most Advanced FinFET Processes

Analog Bits at TSMC OIP – A Complete On-Die Clock Subsystem for PCIe Gen 5


Cadence adds a new Fast SPICE Circuit Simulator

Cadence adds a new Fast SPICE Circuit Simulator
by Daniel Payne on 06-02-2021 at 10:00 am

SPICE spectrum. Fast SPICE

In the early years of Cadence their growth was bolstered through many well-timed acquisitions, however over the last several years I’ve noticed a distinctively different trend where they have internally developed EDA tools. I had a Zoom call with Jay Madiraju from Cadence, who markets their newly announced Fast SPICE tool called Spectre FX, developed internally. We first met back in 2003 while working at another EDA company on their Fast SPICE circuit simulator, so Jay really knows the SPICE market place quite well.

Simulator Family

Cadence now offers three SPICE circuit simulators, each serving a different engineering purpose:

  • Spectre X – Focus on accuracy, analog characterization
  • Spectre FX – Focus on capacity and simulation speed
  • Spectre AMS Designer – Mixed-signal, mixed-language, mixed-level with Xcelium logic simulation

These three circuit simulators now cover the complete spectrum of accuracy, capacity and speed that IC designers need to design and optimize their semiconductor IP for timing and power:

The market segments that Cadence serves can be divided into eight categories, and it’s part of what they call an Intelligent System Design strategy:

  • Consumer
  • Hyperscale
  • Mobile
  • Communications
  • Automotive
  • Aero/Defense
  • Industrial
  • Health

A circuit design engineer using Spectre FX can now quickly simulate some of the largest transistor-level netlists for DRAM, Flash and SRAM memories, because of the high-capacity in a Fast SPICE tool. Interconnect now dominates the speed of a chip, more than the transistor switching, so using a Fast SPICE simulator on post-layout netlists is essential to predicting silicon speed during the design phase.

Tuning

It was at UC Berkeley that the first SPICE simulator was developed, and historically SPICE simulators have used dozens of arcane options to control internal parameters like DC convergence, iteration methods and accuracy settings. Spectre FX takes a different approach by providing default settings that work well for most IC designs, and then letting you decide how to trade-off accuracy for simulation speed with a simple option.

Interactive Simulation

Another vestige of Berkeley SPICE is that most SPICE simulators are purely batch oriented, where you setup the time duration, launch the job, then patiently wait for results. With Spectre FX there’s also the interactive mode of using the tool, so a circuit designer can start a job, pause, make measurements, then optionally decide to save the simulation results as a starting point for a subsequent run, or continue simulating.

Speed and Capacity

Traditional SPICE uses a single, large matrix to simultaneously solve for currents and voltages, while Fast SPICE does automatic partitioning into many, smaller matrixes, and uses event-driven methods between partitions. What makes the Cadence approach unique is the emphasis on exploiting Multi Threading for efficient use on up to 32 cores. The claim is that this approach shows up to 3X faster simulation results than the competitors, and here’s some direct comparisons on six different design types:

Early Customers

It’s a real challenge to get actual customers talking about using a new circuit simulator, because they often don’t want competitors to know how to get faster results and improve time to market. Kudos to Cadence for getting some well-known semiconductor design companies to talk about using Spectre FX, including MediaTek, Renesas and JVCKENWOOD.

Summary

Cadence has filled out their SPICE circuit simulator family to include Fast SPICE in the new Spectre FX tool, and here’s how that fits into the bigger family of EDA tools:

The field for SPICE circuit simulators just got more competition, and that always gives customers better value for their money. Read more about Spectre FX on the Cadence site.

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Fuzzing to Validate SoC Security. Innovation in Verification

Cadence Extends Tensilica Vision, AI Product Line

Agile and Verification, Validation. Innovation in Verification


IP-XACT Resurgence, Design Enterprise Catching Up

IP-XACT Resurgence, Design Enterprise Catching Up
by Bernard Murphy on 06-02-2021 at 6:00 am

IP-XACT Resurgence

This standard has been around in one form or another for over ten years and was then arguably ahead of its time. RTL designers were confused: ‘We already have RTL. Why do we need something else?’ I also didn’t get it. Still, the standard plugged ahead among the faithful and found traction among IP vendors. Particularly as a common format to distribute non-RTL data, like register maps. But a lot has been changing in the meantime. Faster moving competitors. More horizontal and vertical dependencies. Mergers and acquisitions. Chinese technology growth and competition. To adapt, some top-tier organizations have already fully embraced IP-XACT, others are now racing to catch up. Why? Rather than making a dry technical case, I’ll share a few real examples (no names).

A design-out that failed

Semiconductor companies are painfully aware that winning a socket in a top-selling consumer product is a mixed blessing. Once OEMs see their product taking off, they start building their own SoC to reduce cost on the next release. They plan that into their product forecasts and their execs and investors are pleased. But if the in-house SoC misses the product schedule, they must buy the commercial chip again, missing that profitability plan.

This is a very big deal. In one instance senior managers were fired and the company launched an audit. To figure out what went wrong and how to fix it. A major conclusion was that all the integration glue (in-house developed scripts and databases) used in full-chip integration didn’t hold up under pressure. They didn’t have a single robust source of truth for all the dependencies they needed for total product coverage. We all know why. Glue was built on great ideas and enthusiastic internal support. Then someone leaves, or requirements change in a major way, or the expert is fighting another fire. Then we remember why in-house software and databases are brittle and why commercial platforms, in this case for integration, have their advantages.

In this instance, the audit recommended the design team should switch to an IP-XACT source of truth. Which they did, and all other SoC teams in that organization have followed. Now they have a platform which replaces much of that glue. A platform designed for integrity across the enterprise. For design, product engineering, documentation, software. Which they can still extend with their own special features. And since it’s built on a standard, they have security in their investment. Now the commercial SoC option has been designed out and, as far as I know, their product releases have remained on schedule.

Ramping up an ecosystem of startups, fast.

OK you may think. That’s a big company problem, we don’t need that kind of solution. In fact, aside from scale I think these challenges are universal. I would be surprised to hear of any established design team that hasn’t built masses of integration glue. But for grins consider another very real example. In China, regional governments are charged with supporting technology startups. Some of this is through investment funding, some through encouraging synergies between startups.

Synergies in sharing IP and flows for example. They chose to invest in IP-XACT as a common platform to encourage this sharing. Think of the collective power of a bunch of Chinese startups, working together. Great for them. Perhaps a little concerning for the rest of us. Maybe we don’t want to work that closely with competitors (though ‘competition’ is a very different animal these days), but we should probably want to smooth out any friction in our product integration. To not simply hand our Chinese competitors an advantage there as well.

M&A synergies

Big systems companies recruit expert design teams from semiconductor companies. This isn’t news.  The team brings across all their expertise, but they can’t bring the glue. They could build it up again, but that’s not what they’re being paid for. And maybe the people who did most of that work in building the glue weren’t included in the transition.

An easy option in this case is to do the same thing the Chinese startups are doing – build on an IP-XACT platform. Especially if the acquired team already have expertise in that standard. That’s the nice thing about a standard. Some hires/acquires will have that expertise, and this number will most probably grow with time. The pool of people who have expertise a particular class of in-house glue can only shrink over time.

Spot the trend

The range of needs that integration infrastructure must cover will continue to grow. Interoperability with partners. Software interdependencies. Document generation. Traceability. More and more connection to enterprise requirements. No wonder IP-XACT is coming back with a vengeance.

To learn more about Arteris, go HERE.

Also Read:

Architecture Wrinkles in Automotive AI: Unique Needs

Arteris IP Contributes to Major MPSoC Text

SoC Integration – Predictable, Repeatable, Scalable


TSMC 2021 Technical Symposium Actions Speak Louder Than Words

TSMC 2021 Technical Symposium Actions Speak Louder Than Words
by Daniel Nenni on 06-01-2021 at 1:00 pm

TSMC Symposium 2021

The TSMC Symposium kicked of today. I will share my general thoughts while Tom Dillinger will do deep dives on the technology side. The event started with a keynote by TSMC CEO CC Wei followed by technology presentations by the TSMC executive staff.

C.C. Wei introduced a new sound bite this year that really resonated with me and that was “actions speak louder than words”. TSMC has always reminded me that it is important to speak softly and carry a big stick. While this does not always get TSMC the best media coverage it works extremely well with customers, and of course is a key ingredient to the TSMC “World’s Trusted Foundry Partner” strategy. Transparency is another key ingredient and you will not find a more transparent foundry than TSMC.

Who else presents defect density numbers? Which is really where the rubber meets the road for ramping new process technologies. Let me remind you how lucky we are to have C.C. Wei leading TSMC. He is a brilliant technologist and a great leader which is a very unique combination. I fully expect the many CEO awards to come his way in the not too distant future, absolutely.

The keynote was followed by presentations from the executive staff.  Noticeably missing was Cliff Hou who is now Senior Vice President, Europe and Asia Sales. My guess is that direct customer experience is a stepping stone to something bigger for Cliff. That and gray hair.

Learn About:

  • TSMC’s smartphone, HPC, IoT, and automotive platform solutions
  • TSMC’s advanced technology progress on 7nm, 6nm, 5nm, 4nm, 3nm processes and beyond
  • TSMC’s specialty technology breakthroughs on ultra-low power, RF, embedded memory, power management, sensor technologies, and more
  • TSMC’s advanced packaging technology advancement on InFO, CoWoS®, and SoIC and other exciting innovations
  • TSMC’s manufacturing excellence, capacity expansion plan, and green manufacturing achievement
  • TSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design

Y.J. Mii (Senior Vice President, Research & Development) discussed advanced logic technologies, technology innovation beyond 3nm, and advanced integration technologies.

Kevin Zhang (Senior Vice President, Business Development) discussed specialty technology development and offerings.

Y.J. Mii (Senior Vice President, Research & Development) discussed advanced technology value aggregation, design ecosystem readiness for N5-N4-N3, and RF design platform update, and 3DIC design ecosystem for system innovation.

Y.P. Chin (Senior Vice President, Operations) provided a manufacturing update with new capacity ramping and new fab status, advanced packaging and testing operation, and green manufacturing.

This was followed by more technical sessions on advanced technology for smartphone and HPC platforms, 3D fabric technology, advanced RF and analog technology, BCD technologies for PMIC, eNVM and automotive, and ultra-low power technology for IoT platforms.

There is a LOT of information to cover so let us know what you are most interested in and we will prioritize as appropriate. Or ask us questions and we can answer them directly.

Hopefully the other foundries will take this symposium to heart and talk more about actions and how they have helped customers, the environment, and the world of electronics in a transparent manner. Thank you for reading and there is plenty more to come.


IoT’s Inconvenient Truth: IoT Security Is a Never-Ending Battle

IoT’s Inconvenient Truth: IoT Security Is a Never-Ending Battle
by Dana Neustadter on 06-01-2021 at 10:00 am

IoTs Inconvenient Truth IoT Security Is a Never Ending Battle

The continued innovation and widespread adoption of connected devices — the internet of things (IoT) — has resulted in a vast range of conveniences that improve our lives every day. At the same time, the ubiquity of IoT devices, which market watchers estimate to be in the tens of billions, also makes it more attractive to bad actors who see opportunities in the sheer volume of “open doors” that the popularity of IoT offers. At every point, there are vulnerabilities to malicious attacks allowing interception of vital information. For all the advances and automation that IoT enables, security is paramount because it affects both device manufacturers and end users alike.

The number and variety of IoT security attacks have increased as the volume of devices proliferate on networks, even with those that offer the most secure connectivity. IoT security is complex and encompasses many layers involving both hardware and software efforts at all levels of the network, and the rules of the game are constantly in flux. Connected devices operate in an environment where attacks can originate from anywhere and must be capable of adapting to an evolving threat landscape. With the amount and value of data that can be accessed, hackers are becoming increasingly sophisticated in their approaches. AI-enabled attacks are commonplace, for example, as breaches use advanced algorithms to bypass seemingly secure systems and networks.

Security is a fundamental requirement of any connected device, but implementing security solutions is not a “one size fits all” proposition. Different applications have specific needs and restrictions — performance, form factor, power consumption, operating environment, and cost, to name a few. And, of course, the value of the data being processed by the application varies widely. Consider a fitness tracker that only monitors your daily step count compared to a complex healthcare network that contains a trove of highly confidential and personal data; the latter requires higher-grade security and safeguards.

Baking Security in from the Beginning of IoT SoC Design

Every IoT device has security design considerations that must be thought through at the earliest stages of the SoC design process. Minimum requirements such as protection at power on and off, and basic security during runtime and when connected to a network or when devices are communicating with each other, are essential. In addition, designers must consider laws around data protection. For example, there’s the Global Data Protection Regulation (GDPR) in Europe, which imposes steep fines on corporations if private user data is compromised. An example in the U.S. is the Health Insurance Portability and Accountability Act (HIPAA) that stipulates how Personally Identifiable Information (PII) maintained by the healthcare and healthcare insurance industries should be protected from fraud and theft. From there, the specifics of the application and use cases need to be addressed and prioritized, such as what software is being run on the devices, where it is physically located, and the robustness of the authentication and identification needed.

In this post, we’ll offer an overview of two weapons in the battle for secure IoT design.

tRoot Implements a Secure Root of Trust

From an SoC design perspective, security has both hardware and software implications; the engineer’s toolbox requires ways to address both, from RTL design to system verification. A key enabler is pre-verified IP subsystems that can be easily integrated within the SoC to provide a scalable platform for diverse security functions and applications.

The Synopsys DesignWare IP offering includes the tRoot Hardware Secure Module (HSM), which was created specifically for implementing a secure hardware root of trust in connected devices. This solution supports all the essential elements for developing an effective root of trust, which provides a security perimeter for protecting sensitive data and operations. It includes a secure CPU, multiple secure key servers for key transport protection, secure instruction and data controllers to provide external memory access protection and runtime tamper detection, and cryptographic acceleration with protection against side-channel attacks.

A root of trust can be started by a variety of methods, including simply loading its protected memory region and signaling that it has firmware available. Alternatively, it can be loaded using a hardware state machine from external Flash memory, run directly out of SPI memory, or a variety of other methods. When it starts, the root of trust derives its internal keys from supplied device identity inputs and executes self-tests and code validation for itself. If these tests are passed, it can move on to validate code for other subsystems in the chip using a secure bootstrap process.

The root of trust is used to perform several functions, including secure monitoring during power up and runtime operation of the SoC, secure validation/authentication for verifying the validity of the code and/or data on the SoC, storage protection, secure communication, and key management.

tRoot HSM provides robust hardware protection while being highly configurable, flexible, and maintaining a high level of performance. tRoot HSM is used to provide security functions in a trusted execution environment as a companion to a host processor that runs most system applications. To minimize the number of attack vectors, tRoot HSM uses a simple interface with a limited set of interactions with the host processor. At the same time, it provides a fully programmable platform that can offer a variety of services throughout the device’s lifecycle.

tRoot protects IoT devices using unique code protection mechanisms that provide runtime tamper detection and response, and code privacy protection without the added cost of more dedicated secure memory. This unique feature reduces system complexity and cost by allowing tRoot’s firmware to reside in any non-secure memory space.

iSIM Provides Flexible and Adaptable IoT Security

tRoot HSM can be leveraged to implement an evolving security approach that is based on the concept of the familiar SIM card. Mobile operators have been using SIM cards for years to protect their devices and networks from fraud and misuse, and to ensure secure communications for customers.

The traditional SIM card has evolved into new forms, including an eSIM format: a chip that can be soldered on a board instead of a card that is inserted into a SIM card slot. This allows for devices to include the SIM hardware secure element when the device is manufactured. eSIM provides the additional benefit of being able to remotely install and manage the connectivity profile and subscriber identity.

To further address the cost and size requirement of IoT devices, there is a move toward integrated SIM (iSIM), which is implemented not as a separate secure element chip but is instead integrated with the modem or application chip. The technology has led to the successful integration of discrete chips and modules into a single SoC combining the application, modem, and SIM functions.

Synopsys has partnered with several eSIM/iSIM OS and service providers, including Truphone, to provide complete solutions comprised of the hardware, software, and services needed to enable mobile network operators and product manufacturers to securely connect and manage devices in worldwide cellular networks.

SoCs that incorporate iSIM reduce component count, simplify board integration, and enable resource sharing within the chip. Instead of duplicating resources like a memory controller and peripherals for the SIM card or chip, for the application processor chip, and for the modem module, some resources can be shared on-chip between these different subsystems.

Implementing an iSIM can be complex, which is why the ease of integration with tRoot HSM is appealing. Designers who use tRoot HSM can create a trusted execution environment that both logically and physically isolates and shields all processing of the iSIM software stack from other components, like the application processor or direct memory access (DMA) engines that could tamper with the iSIM processing and leak secret keys. In addition to providing a high level of security, the processing is energy- and area-efficient to support the long lifetime of low-cost, battery-powered IoT devices.

IoT Security from the Ground Up

Security is a critical element of IoT deployment, yet it is too often neglected in the early stages of SoC and system development. Applying security as an afterthought can lead to data breaches, especially in the era of intelligent, connected devices. Security must be designed into IoT devices from the very beginning, and manufacturers need to adopt a security-by-design mindset, protecting both their products and their customers’ data starting at the silicon level.

In Case You Missed It

Catch up on other IoT and security news by reading these recent blog posts:


Enabling Silicon Technologies to Address Automotive Radar Trends and Requirements

Enabling Silicon Technologies to Address Automotive Radar Trends and Requirements
by Kalar Rajendiran on 06-01-2021 at 6:00 am

Current GF Nodes Supporting Automotive

During the week of April 19th, Linley held its Spring Processor Conference 2021. The Linley Group has a reputation for putting on excellent conferences. And this year’s spring conference was no exception. There were a number of very informative talks from various companies updating the audience on the latest research and development work that is happening in the industry. The presentations had been categorized under eight different subject matters. The subject matters were Edge AI, Embedded SoC Design, Scaling AI Training, AI SoC Design, Network Infrastructure for AI and 5G, Edge AI Software, Signal Processing and Efficient AI Inference.

Whether a self-driving automobile or one with a person behind the steering wheel, automotive safety is always a topic of wide interest. One of the presentations at the conference addressed this topic from a silicon enablement perspective. The talk was titled “Enabling Silicon Technologies to Address Automotive Radar Trends and Requirements.” It was delivered by Dr. Farzad Inanlou, CTO, Radar and mmWave, AIM Business Unit, GlobalFoundries, Inc.

Automotive segment is a market that has historically been supported by a few select semiconductor suppliers. In turn there are a handful of foundries that have supported these semiconductor products. Of late, more semiconductor companies have been jumping in, attracted by projected revenue growth possibilities. This in turn has increased and accelerated foundry efforts to support this market. Two factors behind this forecasted growth are Advanced Driver-Assistance Systems (ADAS) and autonomous driving market opportunities. Converting the opportunities into profitable revenue depends on how well the application, product and market challenges are overcome.

This blog will first describe the challenges involved to establish the backdrop and then proceed to cover the salient points from Dr. Inanlou’s talk.

Challenges

ADAS and Autonomous Driving Challenges

ADAS is all about sensors, sensing, analyzing, assessing, weighing options, warning and assisting driver’s actions or autonomously taking action. These steps require accurate sensor data, very quick assessment of the hazard, weighing of evasive options and quick action. The sensors need to be capable of long measurement range and should be able to distinguish between signal (generated by actual obstacles) and noise. Environmental and weather conditions make this task more difficult. The sensors data are input to very complex in-car software running AI driven algorithms to decide on the critical actions to be taken. This kind of compute workload calls for high performance, low power solutions.

Semiconductor Solution Challenges

Environmental conditions vary a lot and semiconductor process should enable devices to operate under these conditions and still produce accurate results. As Edge applications, ADAS call for high performance and low power solutions. Traditional microcontroller-based solutions are not a match for this kind of compute workloads.

Automotive Market Driven Challenges

Automotive manufacturers differentiate their vehicle models not only based on performance, reliability, cabin comfort and convenience but also on the appearance and aesthetics of the vehicles. The aesthetics aspect dictates where and how the different sensors are placed on the vehicle. This in turn demands certain operating and performance characteristics as well as the form factor of the different sensors that can be used. And thorough testing of the ADAS solutions is essential to minimize chances for real-life accidents and related human casualties and property damage liabilities.

GlobalFoundries’ Technology

The value of a technology is determined based on a number of criteria. Can the technology implement a particular solution, can it implement the solution easily and efficiently (area, power, performance), can it implement the solution cost advantageously, and does it have a long-term support and technology roadmap? Is the technology a core competency and focus for the supplier? The answer to all of these questions is in the affirmative for mmWave radar technology enabled by GlobalFoundries’ silicon technologies.

Enabling Applications

GlobalFoundries provides three levels of industry-leading solutions to address ADAS and autonomous driving requirements of the automotive market. Refer to Figure below.

  • 22FDX-based radar sensors deliver higher resolution with less latency than current radar sensors while minimizing total system cost
  • 40nm-based solutions deliver excellent image quality and high reliability under a variety of operating conditions
  • SiGe-based solutions support longer range of detection along with excellent image quality

Products Enablement

GlobalFoundries has made it easier for any company to design differentiated mmWave radar solutions. Through a range of offerings that include silicon-verified IP and reference designs, product designers are able to easily optimize chips to support ADAS functionality and get their products to market rapidly.

GlobalFoundries 22FDX technology (for example) is suitable for optimally implementing certain ADAS solutions.

Due to key architectural elements behind the technology (refer to above Figure), 22FDX solution enables (compared to equivalent competitor nodes that use bulk CMOS process)

  • higher resolution, longer range and sensor miniaturization with maximum performance
  • 40% less power consumption
  • 50% higher Power added efficiency (PAE)
  • 20% smaller chip area

Enabling the Automotive OEMs

GlobalFoundries offers a range of services that minimize automotive certification efforts and speeds time to market. It is the first and only foundry to offer world-class in-house mmWave test capabilities (including 80 GHz test) built on 20 years of RF experience. This makes chip verification easier and the production process faster and more efficient, helping customers increase design efficiency and accelerate time to market.

Summary

In his talk, Dr. Inanlou discusses lot of details of how GlobalFoundries’ technology offerings enable semiconductor companies and automotive OEMs to effectively tap into the growth opportunities. He goes into details of what it takes to build a differentiated radar and shares some benchmark performance results of their 22FDX technology against certain 28nm technologies. The talk wraps up with a slide that showcases the breadth and depth of their mmWave radar support. If you are involved in developing products and solutions involving automotive radar, I recommend you register and listen to Dr. Inanlou’s entire talk and then explore with GlobalFoundries.

Also Read:

Machine Learning Applied to Increase Fab Yield

Foundry Fantasy- Deja Vu or IDM 2?

A Perfect Storm for GLOBALFOUNDRIES


From Silicon To Systems

From Silicon To Systems
by Daniel Payne on 05-31-2021 at 10:00 am

digitalization min

The annual Siemens Digital Industries Software user group event was held virtually on May 26th, which made it easy to attend from my home office, although selecting from the list of speakers was a challenge, because they offered 475 sessions, wow. My focus is EDA, so I listened to Joseph Sawicki, the Executive Vice President, IC EDA Siemens Digital Industries Software. His on-demand session was entitled Silicon to Systems: From Vision to Reality. I first met Sawicki at Silicon Compilers in the 1980s, and have followed his career ever since then.

Digitalization

The most visible example of digitalization is seen in three big-name companies that are really systems companies, now with their own silicon products which enable them to offer a wide spectrum of business and personal products and services. These ecosystems are quite successful around the world.

 

Our smart phones are a common example of technology that is powered by silicon, connected to the cloud, running highly differentiated apps, creating multiple sources of revenue streams.

Smart Home

Consumer giant Samsung has a vision for the connected, smart home, only made possible with customized silicon chips, cloud connectivity and mobile apps.

Industrial IoT

Factories are rapidly adopting new IoT technology and infrastructure to more efficiently run their business, even the semiconductor fabs are using robotics to help produce the next generation of silicon chips, where automated equipment with hundreds of sensors are now creating terabytes of data each month that require analytics to provide insight and help engineers make decisions.

Online Collaboration

The pandemic has caused a rapid shift to online collaboration with platforms like: Microsoft Teams, Zoom, Slack, Webex and Skype. Both personal and business usage has skyrocketed for these platforms, all enabled by silicon, connectivity and apps. Before the pandemic it required us to travel around the globe in order to communicate with a wider audience as effectively.

Changes During COVID-19

KPMG did a survey to help quantify how the recent impact of COVID-19 has changed our workplace, and how digitalization is shaping that.

  • 63% increased us of cloud and/or automation technologies
  • 56% reduction in travel
  • 55% permanent work from anywhere
  • 24% revenue improvement for digital manufacturers over past 5 years
  • 22% profitability improvement over 5 years for digital manufacturers

Siemens EDA will use a hybrid approach, where most employees can work from home and only come into the office a few days per week.

Semiconductor Growth Trends

Sensor and actuator annual shipments are now about 30 billion units, connected devices have a 10% CAGR, storage trends and data traffic are growing non-linearly, these are all causing semiconductor sales to grow. The history of silicon drivers over the years are:

  • Industrial
  • PC
  • Cellphone
  • Internet
  • Smartphone
  • Digitalization

Semiconductor revenues are about $500B today, with projections of a $1T market by 2030, where IBS has a 9.9% CAGR forecast to 2030.

Siemens EDA Vision

The response to all of this projected semiconductor growth then comes down to a vision with three themes:

  1. Technology Scaling – new nodes and 3D
  2. Design Scaling – using integration,
  3. System Scaling – validation and the digital twin

There are technology scaling roadmaps in place to 5nm, 3nm and even 2nm. Just over the past 8 years in smart phones the application processors used have seen tremendous change:

  • Four nodes, 28nm to 5nm
  • 36% smaller die size, 137mm2 to just 88mm2
  • 12X increase in transistors, 1 billion to 11.8 billion
  • 10X increase in CPU performance, 144 to 1,587 Geekbench single core
  • 23X increase in GPU performance, 11.8 fps to 278.3 fps

Machine Learning Systems

An example of applying machine learning to IC yield was shown with the Calibre SONR tool, used for predictive design and process insights to accelerate yield ramping.

Even failure data from post-silicon DFT tools can be fed back to yield engineers that help pinpoint where to improve the yield ramp for a new process or a new IC design.

Machine learning is also used in the Solido Variation Designer tool to help design, analyze and verify silicon IP in the presence of silicon variability. No more brute force Monte Carlo, all by using ML.

3D IC and Packaging

Siemens EDA has products used in four areas of 3D IC and packaging:

Systems in package is another trend to watch in the journey from silicon to systems.

Design Scaling

High Level Synthesis (HLS) is a proven way to enable design scaling, like developing AI on the Edge systems with a better performance per watt per dollar. Using C+ and SystemC allows architectural exploration, creating more optimized silicon systems, for AI and video.

Digital place and route is part of physical IC implementation, and with the acquisition of Avatar, now Siemens EDA has a tool for billion-gate designs that can provide a faster time to design closure on advanced nodes.

System Scaling

Model-based design has been going on with IC design for decades now, but new electronic systems have presented tougher validation challenges between hardware, software and applications. Hardware-assisted verification now allows you to boot the OS and run real apps, while monitoring power and looking for safety and security issues.

Virtualized Modeling of Systems

Over one year ago PAVE360 was announced, and it lets you model a real-world environment for automobiles, complete with sensors, actuators, and obstacles. This allows you to simulate billions of miles in a vehicle testing out your ADAS system, virtually.

Even a 5G ecosystem can be modeled for a complete smart factory, all before any radios or systems are even installed.

DFT

Extending DFT to include embedding analytical monitors, reporting about the health of a digital system is now possible. Improved security is enabled by embedded analytics.

Silicon to Systems

Siemens EDA is well positioned to deliver on these three themes of technology scaling, design scaling and system scaling as part of the silicon to systems trend. Joseph Sawicki made a compelling video presentation at the Realize LIVE event, and I look forward to the 2022 event being held in person.

Also Read:

Heterogeneous Chiplets Design and Integration

Siemens EDA Acquires an IP Validation Tool for standard cells, IO and Hard IP

Safety Architecture Verification, ISO 26262


5G Automotive Standards, Licensing Fosters Fast Adoption

5G Automotive Standards, Licensing Fosters Fast Adoption
by Roger C. Lanctot on 05-31-2021 at 6:00 am

5G Automotive Standards Licensing Fosters Fast Adoption

The adoption of 5G technology in the automotive industry is proceeding quietly but rapidly. Indications are that 18 car makers from around the world have committed to the deployment of 5G connectivity but have largely done so without bold public statements.

The reason for this swift embrace of 5G has many dimensions, some of which were reflected in the Qualcomm keynote delivered by Alex Rogers, executive vice president of Qualcomm Technology Licensing at the recent “Beyond the Mobile Phone: Leveraging 5G for Automotive” event at Eurecom. For the first time, Rogers noted, the automotive and telecom industries have collaborated on a set of global standards intended to smooth the path of automotive adoption of this latest wireless network technology.

Inherent in the standards setting process has been the recognition and integration of a wide range of intellectual property supporting the deployment of new, industry-altering applications and network capabilities. Connected cars will benefit from and be transformed by cellular connectivity in ways that will enable new revenue-creating business models while saving lives, and reducing congestion and vehicle emissions.

Nowhere is this collaboration more evident than in the multiple European projects for creating cross-border connected automated driving corridors for testing various 5G applications. The Europe-wide scope of the effort which is matched by similar though not as expansive efforts elsewhere in the world speaks to the recognition that 5G will alter the nature of connected driving.

Says Rogers: “With 5G cellular vehicle-to-everything connectivity – or 5G V2X – cars will be able to communicate directly with other vehicles, pedestrians, and infrastructure to exchange real-time information about road and traffic conditions.

“Cars will be able to share intent, trajectory, and location for more predictable and coordinated autonomous driving – saving time and energy… and reducing crashes and fatalities.

“5G will also enable new in-vehicle experiences for passengers and drivers that are richer and more engaging.

“The fact that the power of 5G connectivity is available to the European automotive industry should not be taken for granted.”

Rogers attributes the successful deployment of 5G to the coordinated standards-setting activities of multiple parties in multiple geographies and to the availability of consistent technology licensing strategies that have facilitated the appropriate compensation of technology creators. Together, technology creators and technology users are bringing new connected car capabilities to market.

The rapid uptake of 5G technology by auto makers reflects the record setting pace of 5G implementation by wireless carriers. Data from Strategy Analytics reveals the pace of 5G deployment by carriers is unprecedented.

For auto makers, 5G brings a lower latency, higher capacity network to the task of connecting vehicles simultaneously adding dedicated capabilities in the form of network slicing and inherent network intuition in the form of predictive quality of service. Together, these elements of 5G are paving a path forward for the integration of wireless cellular technology with safety systems for avoiding collisions and enabling automated driving solutions.

Rogers did express some words of concern regarding the licensing of 5G tech. “It would be unfortunate if… just as Europe rallies around building and rebuilding technology sovereignty in various areas such as semiconductors… it allows existing and extremely valuable technology competence and innovation in mobile to be undermined and eroded.

“As we have discussed in many other forums – and as we will continue to urge – we need to find a reasonable industry solution to licensing essential cellular technology in the automotive space. I believe we can,” he said.

Indeed, the time has arrived for auto makers and IP creators to resolve pending licensing issues as cellular 5G technology begins to redefine the driving experience and transform the economic implications of car connectivity. It would be a shame if unresolved issues were to impede the incredible progress already achieved.


Upcoming Webinar: PUFiot, A NeoPUF-based Secure Co-Processor

Upcoming Webinar: PUFiot, A NeoPUF-based Secure Co-Processor
by Kalar Rajendiran on 05-30-2021 at 10:00 am

PUFiot Applications

Throughout history, people have sought after security as a basic right and expectation within a civilized society. Even as recent as a few centuries ago, things were very simple. Subjects looked to their rulers to provide security for their lives and assets. Assets were mostly hard assets such as jewelry, coins or real estate. Administering security was simple and depended on strong guards who provided security through physical means.

Fast forward to today. Other than the house we live in and the vehicles we drive, most other assets are not physical in nature. Stocks, bonds, intellectual property ownership, fiat currencies, crypto currencies, etc. The list goes on. These assets are secured not by some physical means but rather through encryption and storage in the form of zeroes and ones in electronic form around the world. In other words, security is being provided through a combination of hardware/software solutions. For every security solution that is deployed, cyber criminals are always working to identify a weakness to break-in and steel assets.

Many of us know of or heard of mobile phone Subscriber Identity Module (SIM) cards getting cloned to perform unauthorized acts. The unauthorized act could be taking an Uber or Lyft ride under the guise of someone else. Or it could be a bigger act such as intercepting funds transfer that was meant for someone else, now that services exist to transfer monies based on mobile phone numbers. SIM card cloning is a security breach that all of us can relate to but is just one example to highlight the need for an unclonable solution.

It is in this context that eMemory Technology Inc. will be hosting a webinar that will be very informative and useful for chip designers and system engineers. The webinar is titled “PUFiot: A NeoPUF-based Secure Co-Processor” and is scheduled for June 8th, 2021 (EMEA time zones)/June 7th (Americas time zones). I got an opportunity to preview the webinar content. A number of things caught my attention. Following gives a peek into what to expect in the webinar. Please register for the webinar to learn all the intricate details.

Physical Unclonable Function (PUF)

A PUF can be thought of as a physically defined fingerprint and serve as a unique identify for a physical object. Although there are many different types of PUFs, the focus of the webinar is on PUFs implemented in semiconductors to uniquely identify a chip.

NeoPUF is Ideal PUF

NeoPUF is eMemory’s hardware security technology based on physically unclonable microvariations occurring in the silicon manufacturing process.

An ideal PUF is one that will enable the ultimate in security. For that, the PUF has to have the following characteristics.

Randomness: It has to be truly random and unpredictable

Uniqueness: Yet unique, so there is no duplication from device to device

Robustness: Should operate without errors over all PVT variations

Untraceability: Not provide a means for reverse engineering

Manufacturability: Reliably manufacturable with high yield

Radhard: Continue to function even under radiation exposure

The webinar goes into details of how all of the above characteristics are held by NeoPUF. For example, its true randomness results from the innovation of Quantum Tunneling, a world first. Users can generate truly random sequences for applications with high security requirements.

NeoPUF has also passed the NIST 800-22 test for ideal performance without the need for any data post-processing or data helpers such as error correction codes (ECC).

PUFiot

PUFiot is a high-security PUF-based crypto coprocessor to help chip designers easily adopt robust embedded hardware security functions. It has received the Cryptographic Algorithm Validation Program (CAVP) certification. CAVP is established by the National Institute of Standards and Technology (NIST) for technical verification. The certified security algorithms include AES, CMAC, DRBG, key wrap, SHA2, HMAC, KDF, and ECDSA.

This certification qualifies PUFiot under international security standards to meet the security needs of various application scenarios around the world.

Anti-tampering:

PUFiot provides a solid security boundary for chip protection through multiple analog/digital anti-tampering features built into the technology. It protects both intrusive attacks that may use focused ion beam methods and non-invasive attacks that may use side-channel analysis.

Zero-touch deployment:

By internally generating key pairs and IDs, PUFiot lowers the cost of supporting zero-touch deployment requirements of AI/IoT/5G multi-terabyte networked devices. Thus, it can assist cloud-based application ecosystems in achieving zero-trust compliant security operations.

Supported Security Applications

The webinar covers how the PUFiot solution benefits IOT applications when implementing security. Security solutions need to comply with international security standards and regulations for different applications. The rapid growth in AI driven edge applications and related IoT devices demand anticlone measures. Refer to Figure below for the range of security applications that can benefit from a PUFiot-based solution.

 

Broad Support from Foundries

The NeoPUF technology and PUFiot co-processor IP are supported at TSMC, Samsung, UMC, GlobalFoundries SMIC and other foundries. The technology maintains high stability over a very wide temperature range (-40~175°C). It requires no additional mask layer and the IP can be implemented in a compact size for cost-effectiveness.

Summary

Anyone desiring to design non-clonable solutions for security applications would benefit a lot from attending this webinar. Register here for the “PUFiot: A NeoPUF-based Secure Co-Processor” webinar.

 

 

 

 


Contrast Reduction vs. Photon Noise in EUV Lithography

Contrast Reduction vs. Photon Noise in EUV Lithography
by Fred Chen on 05-30-2021 at 6:00 am

Contrast Reduction vs. Photon Noise in EUV Lithography

The stochastic behavior of images formed in EUV lithography has already been highlighted by a number of authors [1-3]. How serious it appears depends on the pixel size with which the photons are bunched. Generally, though, for features of around 20 nm or less, even 1 nm can have at least a +/- 15% gradient across it, which is still a considerable deviation from the condition for applying the Poisson distribution. Applying a 0.5 nm pixel at least can get below +/- 10%. Using such a pixel size, the noise is readily apparent for 19 nm contacts at 65 mJ/cm2 (Figure 1). Multiple locations are expected to fail to reach the threshold to print in the resist.

Figure 1. Targeting a 19 nm feature width at 65 mJ/cm2. The noise (up to +/- 3 sigma) is significant across the feature as well as different at different feature locations. A 0.5 nm pixel size is used for photon grouping.

The picture becomes even more striking when it is viewed as a 2D feature like a contact or via from above (Figure 2), using the same 0.5 nm x 0.5 nm pixel size.

Figure 2. A 2D top view of the feature in Figure 1. The same printing threshold of 11 photons per 0.5 nm square pixel is used.

This picture shows the incident photon number spatial distribution; the actual absorbed photon number distribution is even more noisy. The black areas are those areas where the actual photon number is not expected to expose the resist. There are many of them within where the feature is expected to print. Clearly, the actual image typically formed in the resist does not resemble this picture. Apparently, some mechanism is able to smoothe out this appearance. The migration of secondary electrons [4] is one. Acid diffusion [5] is another. Although these factors can help smoothe out the roughness, they must operate over scales comparable to the feature size itself. In other words, the resist contrast must be sufficiently blurry to fight the photon shot noise [1]. Smaller features present more noise, which would need more blur. At some point, the contrast reduction from the blur will become prohibitive.

References

[1] https://www.fractilia.com/s/Morestochasticsandthephenomenonofline-edgeroughness_Mack-lnfk.pdf

[2] P. deBisschop and E. Hendrickx, Proc. SPIE 10957, 109570E (2019).

[3] https://www.linkedin.com/pulse/demonstration-stochastic-edge-placement-error-epe-frederick-chen

[4] A. Narasimhan et al., Proc. SPIE 9422, 942208 (2015).

[5] https://www.jstage.jst.go.jp/article/photopolymer/27/5/27_623/_pdf

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