SemiWiki – Page 281 – The Open Forum for Semiconductor Professionals

February 20, 2022March 26, 2023

AMAT – Supply Constraints continue & Backlog Builds- Almost sold out for 2022

AMAT – Supply Constraints continue & Backlog Builds- Almost sold out for 2022
by Robert Maire on 02-20-2022 at 6:00 am
Categories: Events, Semiconductor Advisors, Semiconductor Services

-Production constraints push backlog up $1.3B to $8B
-Looks like $100B in WFE 2022 VS $80B in 2021
-Almost sold out for 2022- Could lead to continued growth 2023
-Insp/metrology up 68% Y/Y- Expect steady growth in 2022

Can’t keep up with demand….

Revenue came in at $6.27B and NonGAAP EPS of $1.89. A very slight beat of about 3 cents on EPS and about $75M on revenues. Guidance was more or less flat with current expectations at $6.35B+-$300M and EPS of $1.90 +-$0.15. Basically Applied remains very much supply constrained due to parts shortages and other issues impacting the industry. As an example of this backlog was up $1.3B to a huge $8B in total

“Close to sold out” in 2022

Perhaps most telling was a simple statement that the company is more or less sold out for 2022. This suggests that they don’y expect constraints to disappear any time soon and they will be constrained for most of the coming year.

They did talk about being up single digits every quarter in 2022 as they work out from under some of the supply constraints. Systems were good at $4.6B and display was OK at $380M. Inspection/metrology was especially hot up 68% Y/Y- Taking share

One of the highlights was the inspection metrology division which was up a huge 68% year over year, far more than any competitor, exactly double KLA’s 34% year over year growth.

Wafer inspection was strong but E-Beam doubled year over year.
Its clear from the numbers that Applied is taking share in this part of the market even more than their core dep and etch.

Inspection/metrology was less impacted by the supply constraints which also helped its huge growth as compared to the rest.

Foundry/logic continues to dominate

Foundry/logic continues to be the biggest driver as foundries need to beef up capacity. We are sure that China and TSMC were a big part of it. Memory spending remains under control and recent price hikes in NAND make us feel more confident about continued reserved memory spend going forward. Foundry/logic tends to use a lot more inspection/metrology which also helps account for the outsize performance there

$8B in backlog should help smooth out numbers

Historically ASML and KLA have shipped out of backlog which allowed them to “dial in ” the numbers more effectively. The main limiting factor is the ability to get parts. Even with those limitations having that much backlog should smooth out potholes in demand.

If backlog continues to grow as the company remains supply constrained we wouldn’t be surprised to get to $10B in backlog.

$100B in WFE in 2022 up from $80B in 2021

Applied is looking for roughly $100B in WFE revenues in 2022 which could be even higher , up to $110B, if it weren’t for the supply constraints. This is versus last years huge $80B.

Given the expected single digit revenue growth throughout the year it looks like maybe $45B in the first half perhaps growing to $55B in the second half as constraints get dealt with

Does 2022 set up continued growth in 2023?

We are certainly in the strongest cycle we have ever witnessed in the semiconductor industry and right now with limits on 2022 its starting to look like those constraints may set up 2023 as a growth year as demand from 2022 falls over into 2023…or maybe not.

Its still very early to tell and we still don’t know when chip shortages will end. Most every cycle we have seen ends with the industry going off a cliff without skid marks. It certainly doesn’t feel like that can happen right now, but it always feels good up until the point when it isn’t.

Right now the industry has enough to deal with in shipping product in 2022 without worrying about which direction we are going in 2023. We think its just way too early to say for certain about 2023 even though early signs are positive.

The stock
Applied came in more or less as expected and guided more or less as expected. Normally this would cause the stock to drop as it wasn’t a “strong beat and raise”, but given that the stocks have retreated a lot in recent weeks, just making the numbers without a disappointment may be cause for a bump up.

We are certainly underwhelmed by the in line performance but enthused about the longer term prospects of a good year. Its not like the stock is cheap as it retreated to a more realistic valuation after being over done for a long time.

We see no super compelling reason to own more and if the stock moved significantly higher on in line results we may be tempted to take more money off the table.

We have been covering the space longer and been involved with more transactions than any other financial professional in the space.

We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors.

We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

Tower Semi Buyout Tips Intel’s Hand

Semiconductor Growth Moderating

The Intel Foundry Ecosystem Explained
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Podcast EP63: The growing importance of interconnect architecture

Podcast EP63: The growing importance of interconnect architecture
by Daniel Nenni on 02-18-2022 at 10:00 am

Dan and Mike are joined by Matt Burns, technical marketing manager at Samtec. Matt focuses on why interconnect architecture has become so important for state-of-the-art system designs. The markets that are driving these requirements, along with the challenges and how to address them are provided.

The discussion concludes with an overview of the types of capabilities Samtec offers to address high-performance interconnect in advanced system designs.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

February 18, 2022April 5, 2022

CEO Interview: John Mortensen of Comcores

CEO Interview: John Mortensen of Comcores
by Daniel Nenni on 02-18-2022 at 6:00 am
Categories: CEO Interviews, Comcores, IP

John Mortensen is the CEO & CCO of Comcores. He has been with Comcores since 2019, and has been leading the commercial function since 2020 and was appointed CEO in early 2021. John is focused on creating the best possible customer experience when you do business with Comcores. An experience where you, as a customer, sense how we constantly strive to develop cutting-edge IP’s, how we make an effort to create value, support you in your technology development, and where you can trust that we do our best to deliver on our promises.

John has 20 years of leadership experience within sales and business development in international companies across many different cultural settings. He has vast experience in connecting capabilities across technical and commercial teams and in using input from customers to influence technology roadmap. In addition, he holds an eMBA from Henley Management College.

What’s the Comcores backstory?
Comcores is a Key supplier of digital IP Cores and IP solutions for digital subsystems. Comcores’ mission is to provide best-in-class, state-of-the-art, quality IP components and systems to ASIC, FPGA, and System vendors. Thereby drastically reducing their product cost, risk, and time to market.

Our long-term background in building communication protocols, ASIC development, wireless networks and digital radio systems has brought a solid foundation for understanding the complex requirements of modern communication tasks. This know-how is used to define and build state-of-the-art, high-quality products used in communication networks.

What problems/challenges are you solving?
Comcores develops and licenses digital solutions for advanced communication systems. Our strong portfolio of Ethernet IP’s, timing solutions and security components enables our customers’ advanced solutions to meet the latest requirements ahead of the competition.

Being an expert in time-sensitive-networking (TSN) and nano-second timing precision, Comcores supports mission-critical projects, accelerates customers’ project development and reduces their hidden risk and cost. Our product portfolio also includes high-speed interconnects, advanced chip-to-chip interfaces, complex radio components and high-performance Ethernet transport solutions.

What markets does Comcores address today?
Comcores’ main markets today are 5G Wireless, Aerospace, Industrial Automation and Automotive. We have a solid background in delivering proven IP solutions to 4G and 5G Networks with a focus on O-RAN fronthaul and remote radio head solutions. Comcores is an active member of the O-RAN Alliance and a number of IEEE workgroups. Our close engagement in research and standardization ensures that Comcores solutions support the latest standards and are prepared for future developments.

Comcores also delivers reliable, high-performance IP core solutions including JESD204, Ethernet TSN, timing solutions to projects within Aerospace and Industrial Automation applications.

What makes Comcores and Comcores products unique?
The quality of our products combined with our agile approach in supporting our customers projects means we find a way to support specific customer requirements when off-the-shelf products are not the best fit.

Our long-term experience in dealing with global tier 1 customers, and servicing customers globally from Asia in the East to Silicon Valley/US in the West is another contributor to our success in being a trusted partner to global leaders in the markets we serve.

What’s next for Comcores? Or What is Comcores’ future direction?
We are strengthening our market position in Time-sensitive-networking (TSN) and timing solutions by adding more plug-and-play subsystem solutions to our portfolio tailored for different applications.

We will also cement our position as the global leader for JESD solutions and will build more chip-to-chip interface IP´s.

Also Read:

CEO Interviews: Kurt Busch, CEO of Syntiant

CEO Interview: Mo Faisal of Movellus

CEO Interview: Fares Mubarak of SPARK Microsystems

February 17, 2022February 22, 2022

Tower Semi Buyout Tips Intel’s Hand

Tower Semi Buyout Tips Intel’s Hand
by Doug O'Laughlin on 02-17-2022 at 2:00 pm
Categories: Events, Semiconductor Services
6 Comments

The rationale behind the Tower Semi acquisition and things to watch out for at Intel’s investor day.

Intel bids for Tower Semi
First I have to quote myself because Tower was an error of omission. In November in a piece that was likely too long for its own good, I mentioned that trailing edge fabs are in a huge position of strength and even called out Tower Semi.

A name that I think is worth looking into, but I don’t really have the bandwidth for at this moment, is Tower Semi. It screams like a strategic asset, and all they’ve been doing for the last 10 years is buying lagging-edge fabs. Keep an eye on that, but for now I still think these aren’t as attractive as just metrology companies in Semicap.

First I think it’s funny because semicap has only gone down since then, and Tower Semi of course got a nearly 50% premium bid. So let’s dive a bit deeper into why Tower Semi is such a strategic asset and why Intel is buying them right now. Let’s start with a brief history of Tower Semi.

Tower Semi – The Fab Partner
Tower Semiconductor’s (formerly TowerJazz) history is a storied one. The beginning of Tower starts in 1993 with National Semiconductor’s divestiture of its Israeli fab in Migdal Haemek, Israel. Tower expanded its Israeli footprint with Fab 2 alongside Fab 1 in 2001.

The real transformational deal that made Tower into who they are today was an all-stock merger with Jazz semiconductor in 2008. Jazz semiconductor actually started as a subsidiary of Conexant and was funded by the Carlyle group. Jazz was taken public by a blank check company (SPAC!) and their fab is the Newport Beach fab.

The next big win was a Panasonic JV that enabled Tower to launch 3 Japanese fabs with Panasonic as the main customer and 49% owner. This JV helped Tower offer 65nm CMOS and 300mm technologies for the first time.

In 2016 they acquired another fab with the purchase of Maxim Integrated’s San Antonio fab. This was a way to offload the Maxim fab to transition to a fab-lite model and helped expand production of 200mm wafers for Tower.

Last but not least is the Agrate Italy fab. Tower Semi partnered with STMicroelectronics in 2021 to share the cleanroom of this fab. Tower has 1/3rd of the cleanroom and helps ramp the cleanroom to higher utilization faster.

A simplified graphic of their fab footprint is below.

Notice the types of deals Tower pursues, they are primarily JVs. Tower is the fab partner for many larger IDMs, and by acquiring Tower, Intel now has a new customer opportunity given the tight integration of JVs. Panasonic is Tower’s largest customer at ~25% of revenue, but there are 5 additional customers that account for 4-11% of sales. Then a long tail after that. The tail in particular is Intel’s opportunity.

I want to last talk about some of the niche products Tower has. They seem to be the leading Silicon Germanium (SiGe) manufacturer in the world, a specialty process that is useful for RF (radio frequency) front end. Tower is also a leader in silicon photonics fabrication.

In Tower’s own words their biggest drivers are RF CMOS, industrial sensors, RF mobile, and RF Infrastructure (datacom photonics). In particular, some amount of power ICs fabbing capability for Intel makes sense, RF CMOS likely is just nice to have, and RF infrastructure aligns almost directly with Intel’s future ambitions.

Notice the technology, the majority of their capacity is at the 200mm wafer sizing. While these fabs are “specialty” products, their 6-inch and 8-inch power capacity is not particularly special. I would say there is a good mix of leading specialties like the 300mm CMOS and SiGe (Silicon-Germanium), but the 150mm and 200mm power is relatively commoditized capacity. So now let’s discuss why Tower is a good fit for Intel.

Intel Foundry Service’s Jump Start
A reminder that Intel is not letting go of its Fab, but rather amplifying its fab capabilities in its “IDM 2.0” strategy. This is a renewed commitment to fabbing Intel’s own products, as well as opening up their fab and PDK (Process Design Kit) to other companies and customers. The thought here is that they can further leverage their large fab footprint and offer highly desired leading-edge foundry services to their customers in a time when companies desperately want more leading-edge capabilities. But where does Tower fit into that given their mostly lagging edge capacity?

I think Tower completes the fab footprint in a holistic sense. Imagine you want to fab something completely custom at Intel. It’s a whole unit of data center compute not just a CPU, with connected custom fabric, some silicon photonics, and of course, its power-hungry (PMICs).

In the current Intel world you could just get the leading edge chip and packaging, but not the rest of the silicon, photonics, or power IC that composes a total system. Imagine trying to buy a car and only being sold the engine and the ability to attach the engine to a car (packaging), that is the current scope of Intel Foundry Service (IFS).

Tower expands this. Now we have a full-service shop. And it’s no surprise actually if you look at their peer Taiwan Semiconductor, which is known for its leading-edge logic. But a closer look shows that 37% of TSMC’s revenue consists of geometries larger than 28nm. So in the case of TSMC, you can go to them and get the full solution. If IFS is to compete for head to head, they need Tower to complete their full solution.

This was discussed on their M&A call:

This combination of leading edge and specialty technologies will position us as a truly global end-to-end foundry. When we launched IFS last March, our customers were overwhelmingly excited to work with us. One of the things that consistently asked me was to add specialty and mature nodes to our portfolio. With Tower, we can honor that request and more broadly serve key market segments.

You can’t have a compelling IFS without making it full service. But more than that I think one of the biggest benefits is adding a new culture that is actually customer-centric. Some of the past critiques of Intel’s foundry plans were inflexibility and non-standard workflows.

Working with Intel in the past was like showing up at someone else’s garage and being forced to use their wacky tools and blueprints not being given much insight into how things were made. Tower has standard workflows and a more customer-centric fab culture, and this could be a huge kickstart to creating a standard workflow at IFS.

Yes. And while some of this is premature to talk about it too much detail, given the regulatory process, my expectation is that we will fully merge IFS and Tower into a single foundry business for Intel going forward. And part of the value and the synergy of the acquisition as the question suggest, is to fully benefit from that decades of experience that Tower brings and how to run a global foundry customer-centric business for our customers for the future. So overall, we’ll lay out more of that integration strategy as we get to the time of deal closure. But this will become one foundry business that will be the full integration of IFS today with Tower today.

So assuming IFS and Tower are all one unit, I am now warming up to a foundry spin. It was directly in opposition to what Pat Gelsinger has said before, but let’s examine it from the perspective of Gelsinger’s history and what he knows, aka the Dell corporate structure.

Intel Might Spin Foundry Now
I have followed the Dell complex (for lack of better words) at a surface level for a few years now. Michael Dell, the founder of the PC giant Dell, took Dell private in an audacious LBO with Silverlake. Pat Gelsinger worked at one of the subsidiaries at the time, and the subsequent corporate structure is likely familiar to Pat. While I don’t think Pat Gelsinger is going to take the Dell route it’s good to look at the corporate patterns and behaviors he knows best.

For context, Pat Gelsinger joined EMC as COO in 2009 and has watched the entire Dell structure emerge. This included the EMC collapse into Dell and the spinout of VMWare back to public markets. I’m sure he’s well versed in the logic of spin-offs and tracking stocks that were used at Dell. In fact, you can argue that the partial spin of Mobileye looks a lot like something Dell did with Vmware originally. I now think that this is what will happen in some capacity with Intel Foundry Services.

I don’t think this happens immediately because of the huge capital requirements of IFS, but I do think that post Mobileye spin, the promise of an IFS will be a carrot held over investors’ heads. IFS will be a completely separate unit, and now it has a history of financials and some kind of internal structure that it will inherit from Tower. It’s primed to spin.

I think that it will be mentioned as a “strategic option given market conditions” and broken out segment-wise. This will force investors to start to consider Intel as a SOTP valuation first and foremost. I know that this seems like a headache but Pat’s primary focus is likely on the technology side of things, and it’s easy to slip into what he knows corporate structure-wise. Especially when it enriched the Dell CEO so much. And having that potential option is going to be a valuable card to play in my opinion.

Intel would become a quasi holding company in this scenario, with partial stakes in faster-growing businesses (MBLY, IFS) while its core fabless business itself would be likely a slower growth entity that gets to benefit from its partial stakes in these tracking stocks. This sounds frankly the future of Intel. Now let’s move on to what to expect from Investor day.

Subscribe to Fabricated Knowledge

Intel’s Investor Day
I am for one excited for Investor day. Here are a few of the things I expect:

Resegments and new long term models for each segment

An absolute kitchen sinking of FY22 numbers

Guide up revenue marginally

Gross margins sub 52%

Guide down earnings

Some kind of FCF guide

An aggressive Capex plan, possibly matching TSMC

Mobileye discussion, and the hint of spinning IFS eventually

Progress reports on their catch up plan

They will promise performance parity in 2023

I’m almost certain I will be surprised by something they have. I expect some kind of product announcement, and in particular, I would love to hear more about their DPU.

I wanted to make a bingo sheet but didn’t have exactly enough time. I’ll be watching and live-tweeting the whole event on @_fabknowledge_

I will of course be drinking every time Pat says something horny, e.g. “puberty” at Intel, or “lusts” for fabs. But I’m excited about a good show and have to say, I am the most bullish I have been on Intel in a while. I think there is a chance they can really surprise us, and while I know that the FY22 numbers are about to get brought down, I believe that most investors already know this. Everyone knows that, and in recent days every expected miss has been reversed. I expect that to happen at Intel.

Also Read:

The Rising Tide of Semiconductor Cost

How France’s Largest Semiconductor Company Got Stolen in Plain Sight

TSMC Earnings – The Handoff from Mobile to HPC

February 17, 2022December 27, 2023

CEVA Fortrix™ SecureD2D IP: Securing Communications between Heterogeneous Chiplets

CEVA Fortrix™ SecureD2D IP: Securing Communications between Heterogeneous Chiplets
by Kalar Rajendiran on 02-17-2022 at 10:00 am
Categories: Ceva, Chiplet, IP

Discussions of chiplets has been on the rise, ever since the slowdown of Moore’s law benefits. Gartner Research projects semiconductor revenue from systems using chiplets to grow from $3.3 billion in 2020, to $50.5 billion in 2024. With any market opportunity, there are always challenges to overcome in order to realize the full potential. The chiplets market opportunity is no exception. Consequentially, a lot of development is happening to successfully support chiplets based design, methodology and integration.

First things first. What are chiplets? Chiplets are the multiple smaller dies we end up with after architecturally disintegrating a large integrated circuit or a SoC. Conceptually a chiplets-based design resembles a Silicon-In-Package (SiP) based design. SiP-based approach was historically adopted primarily for faster time to market by mixing and matching dies of pre-existing chips. And, typically the pre-existing chips are from the same vendor. While the mixing and matching part is true with chiplets too, the full market opportunity lies with heterogenous chiplets integration. Heterogeneous in this context means chiplets from different vendors. This aspect in itself raises lots of concerns with adoption, system security being one of them.

CEVA’s recently announced Fortrix SecureD2D IP addresses the above concern by securing die-to-die communications between chiplets in a heterogeneous SoC (HSoC). CEVA is well known for its technologies in wireless connectivity, smart sensing and sensor fusion, AI & Deep Learning, computer vision and audio processing. The Fortrix IP expands CEVA’s offerings into the system and IP platform space.

Before we diving into the details of the Fortrix IP, there is an interesting story to share about the early origins of this IP.

Over the recent past, the slowdown of Moore’s law benefits has been limiting the adoption of SoCs by the defense sector too. Realizing this, the Department of Defense (DoD) had launched the CHIPS program a few years ago. CHIPS stands for Common Heterogeneous Integration and Intellectual Property Reuse Strategies. The vision for this program was to conceive an ecosystem of discrete, modular, reusable IP which can be assembled into a secure system. For example, with a chiplets implementation, how to ensure die-to-die communications are safe and secure? How to guarantee a secure boot and protect against counterfeit chiplets? How to protect against firmware tampering? With the semiconductor supply chain distributed across the globe, possible breach of security and trust is a real concern. On the successful completion of the CHIPS program, DoD launched the SHIP program. SHIP stands for State-of-the-art Heterogeneous Integration Prototype.

Intrinsix (now a wholly-owned subsidiary of CEVA) customized the Fortrix SecureD2D IP for the SHIP program. If there is one industry that literally lives and breathes security and trust, that would be the defense industry. The Fortrix IP is now available for both commercial and defense oriented applications.

CEVA Fortrix SecureD2D IP Solution

The CEVA Fortrix^TM is a hardware/software platform for developing secure chiplet based systems. The Fortrix SecureD2D IP offers secure authentication and firmware boot/code load between chiplets, and ensures system level security in a HSoC. The solution consists of a controller communicating over a secure fabric to hardware-based crypto accelerators. The accelerators support rapid encryption and decryption of functions including ECDSA, SHA2, and AES. The controller is embedded in all the chiplets within the HSoC.

Fortrix Controller Block Diagram

The chiplet containing the system host can be either an ASIC or an FPGA. The firmware for the companion chiplets is stored in a protected area of the host chiplet. A dedicated SPI bus connects the chiplets for establishing a crypto-secure channel. After authentication of the companion chiplet, the encrypted firmware is sent from the host to the companion chiplet. The Fortrix IP platform comes with a low-level API and a sample application for quick and easy customization of the IP.

Refer to the following block diagram to see how the chiplets are integrated within a HSoC.

HSoC Architecture Block Diagram

Benefits of Fortrix IP Platform

Protects against various security threats
Allows for threat protection expansion as threats evolve
Ease of incorporation into a HSoC
Efficient Crypto engines are very efficient in terms of compute cycles and power consumption

IP Availability

Fortrix SecureD2D IP is available for licensing today. Deliverables include RTL, SDC constraints, firmware and documentation. Customers desiring integration services can tap into CEVA’s design services offering for a full HSoC design and delivery.

You can read the full press release about the Fortrix IP here. You can learn more about it at the product page.

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AI at the Edge No Longer Means Dumbed-Down AI

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Ultra-Wide Band Finds New Relevance

February 17, 2022May 4, 2022

Semiconductor Growth Moderating

Semiconductor Growth Moderating
by Bill Jewell on 02-17-2022 at 6:00 am
Categories: Semiconductor Intelligence, Semiconductor Services

The global semiconductor market in 2021 was $555.9 billion, according to WSTS data released by the Semiconductor Industry Association (SIA). 2021 increased 26.2% from 2020, the largest annual increase since 31.8% in 2010, eleven years ago. We at Semiconductor Intelligence track publicly available semiconductor market forecasts and award a virtual prize for the most accurate forecast for the year. The criteria are a forecast publicly released anytime between November of the prior year and the release of January data from WSTS (generally in early March). The winner for 2021 is Future Horizons with an 18% forecast released in January 2021. Malcolm Penn of Future Horizons is a perennial optimist, usually calling for higher growth rates than other forecasters. For 2021 he was closest to being right. Runner-ups are 14% forecasts by us at Semiconductor Intelligence and by Evercore LSI. Most forecasts for 2021 made prior to March 2021 were in the range of 8% to 14%.

What is the outlook for 2022? Who will win the virtual forecasting prize next year? Recent forecasts for 2022 semiconductor market growth range from 9% from WSTS to 15% from us at Semiconductor Intelligence. Future Horizons is less optimistic for 2022 than for 2021, with a 10% projection based on a downturn beginning in 4Q 2022.

Revenues of the top semiconductor companies were generally strong in 4Q 2021. Non-memory companies grew revenues 7% in 4Q 2021 versus 3Q 2021. The strongest growth was from Qualcomm at 14%, AMD at 12% and STMicroelectronics at 11%. All other non-memory companies had revenue increases ranging from 3% to 8%. The weighted average guidance for 1Q 2022 for the non-memory companies is a 1% decline from 4Q 2021. Excluding Intel, which is expecting a 6% decline, the non-memory companies expect 2% growth in 1Q 2022 versus 4Q 2021. Most companies indicate continuing supply chain problems, with overall demand still exceeding supply.

The memory companies (Samsung, SK Hynix, Micron Technology and Kioxia) collectively had a 5% decline in revenue in 4Q 2021 versus 3Q 2021. SK Hynix and Kioxia had revenue gains while Samsung and Micron had revenue declines. The memory companies generally see strong demand, but shortages of other components are hampering the production of some electronic equipment and the demand for memory in these products.

The first quarter of the year typically shows a revenue decline from the fourth quarter of the prior year. Over the last ten years, 1Q has declined from 0.5% to 15% from 4Q – except for 1Q 2021 which was up 3.8% from 4Q 2020. With many companies guiding growth in revenue in 1Q 2022, the outlook for the year 2022 is healthy. We are projecting 1Q 2022 will be flat to down slightly from 4Q 2021. Growth in 2Q 2022 through 4Q 2022 should be moderately healthy as capacity shortages continue to be worked out. Thus, we at Semiconductor Intelligence feel reasonably confident with our 15% forecast for 2022.

Looking beyond 2022, many factors come into play. Most semiconductor shortages are expected to be resolved by 2023, leading to a more balanced market. Global economies should be back on track by 2023, with either the end of the COVID-19 pandemic or the world learning to manage COVID-19 while maintaining relatively normal economic activity.

The International Monetary Fund (IMF) January forecast calls for 4.4% global GDP growth in 2022. Global GDP grew 5.9% in 2021 in a bounce back from a pandemic driven downturn in 2020. The IMF expects global GDP growth to moderate to 3.8% in 2023 – close to the long-term trend – as economies return to more normal activity. IDC projects smartphones growth will moderate from 5.3% in 2021 to the 3% to 4% range in 2022 to 2024. IDC forecasts PCs will decline 1.1% in 2022 following pandemic-driven boom growth of 14.8% in 2021. PCs are expected to grow in the 1% to 2% range in 2023 to 2024, again close to the long-term trend.

The automotive market has been hard hit by parts shortages in the last year. Statista estimated 2021 light vehicle production growth of 8% in 2021, but growth would have been higher if more parts had been available. Parts shortages should persist into 2022 with some easing by 2023. Statista projects strong growth of 9% in 2022 and 11% in 2023 as automotive suppliers respond to pent-up demand. Growth is pegged at 6% in 2024, returning closer to normal trends

IC-Insights predicts the semiconductor market will return to recent long term growth trends, with a compound annual growth of 7.1% from 2021 to 2026. At Semiconductor Intelligence, we expect 2023 semiconductor market growth in the high single digits – in line with historical trends.

Also Read:

COVID Still Impacting Electronics

2021 Finishing Strong with 2022 Moderating

Semiconductor CapEx too strong?

Podcast EP62: Exploring the VSORA architecture

Podcast EP62: Exploring the VSORA architecture
by Daniel Nenni on 02-16-2022 at 10:00 am

Dan is joined by Jan Pantzar, VP sales and marketing of VSORA, a provider of high-performance silicon intellectual property (IP) and chip solutions for artificial intelligence, digital communications and advanced driver-assistance systems (ADAS) applications based in France.

Dan and Jan explore the VSORA architecture that uniquely combines DSP with machine learning acceleration and high-bandwidth memory-on-chip. Current and future use in applications such as self-driving cars are explored.

https://www.vsora.com/

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

February 16, 2022March 9, 2022

Dynamic Coherence Verification. Innovation in Verification

Dynamic Coherence Verification. Innovation in Verification
by Bernard Murphy on 02-16-2022 at 6:00 am
Categories: AI, Cadence, EDA

We know about formal methods for cache coherence state machines. What sorts of tests are possible using dynamic coherence verification? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO) and I continue our series on research ideas. As always, feedback welcome.

The Innovation

This month’s pick is McVerSi: A Test Generation Framework for Fast Memory Consistency Verification in Simulation. The paper was published in the 2016 IEEE HPCA The authors are from the University of Edinburgh.

This is a slightly dated paper but is well cited in an important area of verification not widely covered. The authors’ goal is to automatically generate tests for multicore systems which will preferentially trigger consistency errors. Their focus is on homogenous designs using Gem5 as the simulator. Modeling is cycle accurate; in similar work CPU models may be fast/virtual and coherent network/caches and pipelines are modeled in RTL running on an emulator.

The method generates tests as software threads, one per CPU, each a sequence of loads, modifies, stores and barrier instructions. Initial generation is random. Tests aim to find races between threads where values differ between iterations, i.e. exhibit non-determinism. The authors argue that such cases are more likely to trigger consistency errors.

The authors then use genetic programming to combine such non-deterministic test components from sequences. From these they build new sequences to strengthen the likelihood of races which are likely to fail consistency tests. Where they find inconsistencies, they run a check to classify these as valid or invalid per the memory consistency model. They have a mechanism to measure coverage to guide the genetic algorithm and to determine when they should stop testing.

The authors describe bugs that such a system should find in a cache coherent network and their method performs well. The authors note limitations of formal methods to early and significantly abstracted models. In contrast this method is suitable for full system dynamic coherence verification.

Paul’s view

Memory consistency verification is hard, especially in pre-silicon. But it is a very important topic that we find increasingly center stage in our discussions with many customers.

The heart of this paper is a genetic algorithm for mutating randomized CPU instruction tests to make them have more and more race conditions on memory writes and reads. The authors achieve this using a clever scoring system to rank memory addresses based on how many read or write race conditions there are on that address in a given test. Read or write instructions on addresses scoring high (which they call “racey”) are targeted by the genetic algorithm for splicing and recombination with other tests to “evolve” more and more racey tests. It’s a neat idea, and it really works, which is probably why this paper is so well cited!

The authors benchmark their algorithm on a popular open-source architecture simulator, Gem5, using the Ruby memory subsystem and GARNET interconnect fabric. They are able to identify two previously unreported corner case bugs in Gem5, and also show that their clever scoring system is necessary to create tests racy enough to catch these previously unreported bugs. Also, the authors show that their algorithm is able to find all other previously reported bugs much faster than other methods.

Overall, I found this a thought-provoking paper with a lot of detail. I had to read it a few times to fully appreciate the depth of its contributions, but it was worth it!

Raúl’s view

Our October 2021 article, RTLCheck: Verifying the Memory Consistency of RTL Designs addressed memory consistency by generating assertions and then checking them. This is a different approach which modifies the well-known constrained random test pattern generation by generating the tests using a genetic algorithm with a particularly clever “selective crossover”.

They run experiments for the x86-64 ISA running Linux across 8 cores. The cores they model as simple out-of-order processors, with L1 and L2 caches. Tests run in 512MB of memory with either 1KB or 8KB of address range. Each test runs 10 times. Three experiments run: pseudo randomly generated tests, genetic without selective crossover, and genetic with selective crossover. The evaluation detected 11 bugs, 9 already known and 2 newly discovered. Within 24 hours only the full algorithm (at 8KB) finds all 11 bugs, the other approaches find 5-9 bugs. The full algorithm also beats other approaches in terms of coverage for MESI and TSO-CC (cache-coherence protocols). However this is by a small margin.

The paper is highly instructive although a challenging read unless you’re an expert in MCM. The authors provide their software in GitHub, which no doubt encouraged subsequent papers which cite this work 😀. Given enough expertise, this is certainly one arrow in the quiver to tackle full system memory consistency verification!

My view

As Raúl says, this is a challenging read. I have trimmed out many important details such as memory range and stride. Also I skipped runtime optimization, simply to keep this short summary easily digestible. Methods like this have an objective to automatically concentrate coherency suspects in a relatively bounded testplan. I believe this will be essential to dynamic coherence verification methods to catch long-cycle coherence problems.

Also read:

How System Companies are Re-shaping the Requirements for EDA

2021 Retrospective. Innovation in Verification

Methodology for Aging-Aware Static Timing Analysis

February 15, 2022March 26, 2023

Intel buys Tower – Best way to become foundry is to buy one

Intel buys Tower – Best way to become foundry is to buy one
by Robert Maire on 02-15-2022 at 10:00 am
Categories: Intel Foundry, Semiconductor Advisors, Semiconductor Services
7 Comments

-Intel jumpstarts foundry model with Tower semi buy @$54B Gets complementary tech to round out offerings
-Approval based on satisfying China’s needs as well
-Margin concerns overblown- Will it be allowed to flourish?

Intel pays up to get foundry and technology….

Intel announced a $5.4B acquisition of Tower Semiconductor in Israel. This amounts to $53 per share for a company whose last trade was $33 per share or a whopping 60% premium.

Intel is getting a very well run company that has been a foundry for a long time as well as technology that it currently does not offer that will add to a broader foundry offering other than just bulk CMOS.

In addition the company gets more China business as well as military business both of which are needed to support Intel’s strategic direction. In essence this deal covers multiple birds with one stone which likely accounts for the premium.

Margin concern is overblown and wrong way to look at it

On the conference call a number of analysts seemed to be negative on the acquisition due to Towers lower margins. Most any company acquired by Intel is going to have lower margins and being a smaller player of older technology in the land of giant TSMC is not easy on margins.

We don’t think Intel is buying the business for its margins or financials or as a “bolt on” but obviously for its current positioning as a foundry with complementary technology to Intel. If Tower can help Intel’s core become a more competent foundry than that is more than worth the acquisition price alone.

Will Intel let it succeed?

The main reason Intel previously failed in the foundry business was that the upstart foundry group was smothered by the larger IDM corporate mentality. The current foundry effort is relatively weak as Randhir Thakur has never run a foundry or anything close. Our hope is that the management of Tower becomes the more dominant partner rather than being suppressed. In this way Intel can try to get what it paid for… expertise.

Corporate antibodies are strong in this one and Pat Gelsinger may have to take steps to make it so.

We like Tower and its management

We view Tower as a tough, smart, scrappy company in the model of many other Israeli companies. It has been cobbled together over the years out of a string of deals and acquisitions for little to no money that has followed a much different model.

We have known the CEO, Russell Ellwanger since his days at Applied Materials and think he has done a great job. If Tower’s mentality and methods can be set loose in a much larger company with large resources they might get a lot done.

A limited commodity

There aren’t that many foundries in the world that Intel could buy that would potentially make a difference and make sense.

We view Tower as a somewhat smaller but better, and more profitable version of Global Foundries. Global was cobbled together through a number of acquisitions and stumbled badly in mainstream CMOS and is now also trying to avoid the big dogs (like TSMC) by doing “specialty” silicon. AbuDhabi poured a ton of money into GloFo which is barely break even where Tower was more of a bootstrap operation that is solidly profitable. We think that Intel might have been interested in GloFo until its IPO priced it out of that possibility (but Intel could get a second chance)

Could China have been in the mix?

We would certainly have not been surprised if China was taking a hard look at Tower. China has been sniffing around a number Israeli based technology companies because of its concern about being cut off from US technology as well as CFIUS restrictions on foreign investment/acquisition which makes Israeli acquisitions much easier.

The very high premium could also be signs of a behind the scenes bidding war or wishing to avoid someone else (like China) coming in to outbid Intel after the deal was announced.

Technology is needed and complementary

The technology side should be a no brainer for Intel….just let it run and don’t screw with it. Most of the processes that Tower runs harken back to Gelsingers earlier stint at Intel and most of those Intel people took the buy out long ago, so Tower knows the tech better than Intel does.
Intel can likely help with some older equipment and fabs it has lying around and Tower could easily contribute to equipment reuse. Tower could likely get a ton of benefit from what Intel has written off.

The stock

While we view this deal very positively and a step in the right direction, it has to be approved first, which will likely take at least a full year and then be integrated (or not).

For Intel we think its a great trade to sell off the crummy memory business and get a foundry business in trade…it just makes sense.

We don’t see this as a reason however to run out and buy the stock of Intel as the impact will take years but we do see it supporting the longer term strategy.
We will likely hear more at Intel’s investor day this Thursday… In the presentation “Goliath buys David”.

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Also read:

The Intel Foundry Ecosystem Explained

Intel Embraces the RISC-V Ecosystem: Implications as the Other Shoe Drops

The Semiconductor Ecosystem Explained

February 15, 2022February 21, 2022

The Intel Foundry Ecosystem Explained

The Intel Foundry Ecosystem Explained
by Daniel Nenni on 02-15-2022 at 5:00 am
Categories: Events, Foundries, Intel Foundry
12 Comments

Exciting times for the semiconductor industry! Last week Intel announced a billion dollar fund to build a foundry ecosystem and today Intel announced they are acquiring foundry Tower Semiconductor for $5.6 billion dollars, WOW! Some people doubted Intel’s commitment to the foundry market this time. I think we can now put that to rest. Intel is in the foundry business, period.

First let’s talk about the billion dollar ecosystem investment:

How It Works: As a key part of its IDM 2.0 strategy, Intel recently established IFS to help meet the growing global demand for advanced semiconductor manufacturing. In addition to providing leading-edge packaging and process technology and committed capacity in the U.S. and Europe, IFS is positioned to offer the foundry industry’s broadest portfolio of differentiated IP, including all of the leading ISAs.

A robust ecosystem is critical to helping foundry customers bring their designs to life using IFS technologies. The new innovation fund was created to strengthen the ecosystem in three ways:

Equity investments in disruptive startups.
Strategic investments to accelerate partner scale-up.
Ecosystem investments to develop disruptive capabilities supporting IFS customers.

Who’s Involved: The IFS Accelerator features innovative partner companies across each of the three pillars of the program:

EDA Alliance: Ansys, Cadence, Siemens EDA, Synopsys
IP Alliance: Alphawave, Analog Bits, Andes, Arm, Cadence, eMemory, M31, SiFive, Silicon Creations, Synopsys, Vidatronic
Design Services Alliance: Capgemini, Tech Mahindra, Wipro

Richard Wawrzyniak did a nice explanation of the RISC-V investment (Intel Embraces the RISC-V Ecosystem: Implications as the Other Shoe Drops) so let’s continue with the EDA, IP, and Design Services sections.

EDA is an easy one for Intel as they are the biggest consumer of EDA tools. In fact, Intel is one of Synopsys’ largest customers, if not THE largest. And since Synopsys is also the largest IP vendor this relationship is critical. So, EDA is important but not a big challenge since Intel is already tight with the EDA community.

IP is a similar situation for Intel. There are already relationships with the commercial IP vendors through the TSMC based business. Remember, Intel historically uses TSMC for 20% of their production soon to be increased to more than 50% with N3 so there is a lot of TSMC based commercial IP floating around Intel already. Opening that up to Intel specific processes should not be a hard thing to do and that is where the billion dollars is going, to get that IP silicon proven on Intel processes and packaged up for foundry customers. According to the IP ecosystem, they are already gearing up to port military grade IP to Intel processes.

The big weakness I saw in the announcement is the Design Services Partners. Design services plays an important role inside the foundry ecosystem. I had once suggested that Intel buy a big ASIC company to closely partner with like TSMC and GUC, UMC and Faraday, or SMIC and VeriSilicon.

Of course, now that Intel is buying Tower Semiconductor for $5.6B that disrupts the ecosystem quite a bit:

Tower’s expertise in specialty technologies, such as radio frequency (RF), power, silicon-germanium (SiGe) and industrial sensors, extensive IP and electronic design automation (EDA) partnerships, and established foundry footprint will provide broad coverage to both Intel and Tower’s customers globally. Tower serves high-growth markets such as mobile, automotive and power. Tower operates a geographically complementary foundry presence with facilities in the U.S. and Asia serving fabless companies as well as IDMs and offers more than 2 million wafer starts per year of capacity – including growth opportunities in Texas, Israel, Italy and Japan. Tower also brings a foundry-first customer approach with an industry-leading customer support portal and IP storefront, as well as design services and capabilities.

What isn’t mentioned is military embedded systems. Tower is perfectly positioned for US military aerospace and defense contracts and I can assure you that is part of the Intel strategy. Jazz Semiconductor, formerly Rockwell, is a key part of this transaction, More leverage for CHIPs Act money, absolutely.

Jazz Semiconductor Trusted Foundry (JSTF), a wholly owned subsidiary of Tower Semiconductor Newport Beach, Inc., was created and accredited as a Category 1A Trusted Supplier by the United States Department of Defense’s (DoD’s) Defense Microelectronics Activity (DMEA) as a manufacturer of semiconductors that may be used in trusted applications. In addition, as of October 2014, JSTF has been accredited with Category 1B.

JSTF joins a small list of companies accredited by the DoD Trusted Program, established to ensure the integrity of the people and processes used to deliver national security critical microelectronic components, and administered by the DoD’s Defense Microelectronics Activity (DMEA). JSTF is proud to join the DoD Trusted Program to enable trusted access to a broad range of on-shore technologies and manufacturing capabilities.

The Intel investor call is getting ready to start. I will add more thoughts in the comments section.

Also read:

Intel Discusses Scaling Innovations at IEDM

Intel Architecture Day – Part 1: CPUs

Intel Architecture Day – Part 2: GPUs, IPUs, XeSS, OpenAPI