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S2C EDA Delivers on Plan to Scale-Up FPGA Prototyping Platforms to Billions of Gates

S2C EDA Delivers on Plan to Scale-Up FPGA Prototyping Platforms to Billions of Gates
by Daniel Nenni on 11-08-2021 at 6:00 am

S2C has been a global leader in FPGA prototyping for nearly two decades now, and its FPGA prototyping platforms have closely tracked the availability of the latest FPGAs – including the latest FPGAs from both Xilinx and Intel.  And they are definitely delivering on the promise to advance their prototyping solutions for hyperscale design prototyping – scaling-up prototyping platform capacities and capabilities to support multi-billion gate designs.

Looking back to early 4Q 2020, S2C announced support for the then-new Xilinx VU19P UltraScale+ FPGAs, offering single, dual, and quad FPGA prototyping platforms.  Then, in December of 2020, S2C followed-up with an announcement of its high-density Prodigy Logic Matrix family of prototyping platforms with 8 FPGAs per Logic Matrix, 8 Logic Matrix per single server rack (64 FPGAs), and the connection of multiple server racks together.  The first iterations of Logic Matrix were delivered with Xilinx VU440 FPGAs (dubbed the LX1) to early customers who couldn’t wait for the VU19P version (dubbed the LX2).

Now, S2C is stepping up its Logic Matrix game with the LX2, which jumps prototyping usable gate capacity by 60% over than the VU440 version!  More usable gates per FPGA means fewer FPGAs, fewer FPGA interconnects, and higher performance for the same prototyped design.  With an estimated gate capacity of 392 million gates per LX2, a fully populated standard server rack with 8 LX2’s enables an estimated prototyping capacity of over 3 billion ASIC gates!

Prodigy Logic Matrix LX2

Figure 1: Prodigy Logic Matrix LX2

Prodigy Logic Matrix Family
LX1 LX2
FPGA XCVU440 XCVU19P
Estimated ASIC Gates (M) 240 392
Number of FPGAs 8 8
System Logic Cells (K) 44,328 71,504
FPGA Memory (Mb) 709 1,327.2
DSP Slices 23,040 30,720
External User I/Os 9,216 10,368
 SerDes Transceivers 384 GTH 640 GTY
Prodigy Connectors 64 72
PGT Connectors 8 0
Transceiver Connectors 80 MSAS each with 4 GTH + 8 IOs 160 MCIO each with 4 GTY + 8 IOs
SerDes Performance 16 Gbps 28 Gbps

Prodigy Logic Matrix Family

Figure 2: Logic Matrix Family

Flexible, high-speed interconnect is key to high-density FPGA prototyping, and Logic Matrix supports a hierarchical, 3-level interconnect strategy: ShortBridge for interconnect between neighboring FPGAs; SysLink for high-bandwidth FPGA cable interconnect, and TransLink for longer distance FPGA SerDes interconnect over MCIO cables.  To simplify FPGA interconnect and maximize the value of TransLink, S2C’s partitioning flow supports Xilinx’s newly introduced High-Speed Transceiver Pin Multiplexing (HSTPM), simplifying cycle-accurate signal transfer, pin-multiplexing, and low-latency SerDes FPGA connectivity.

To minimize time-to-prototyping, and maximize prototyping productivity, S2C’s other prototyping productivity tools are designed with Logic Matrix in mind, including Player Pro Runtime software – and add-on S2C prototyping tools including ProtoBridge, MDM Pro, and S2C’s Prototype Ready IP.

Player Pro Runtime software is included with LX2, providing convenient features such as advanced clock management, integrated self-test, automatic board detection, I/O voltage programming, multiple FPGA downloads, and remote system monitoring and management.  Also included is AXEVision, a built-in AXI-over-Ethernet debugging tool to simplify remote debugging of AXI related designs.

ProtoBridge supports high-throughput data transfers (up to 1GB/s) between the host PC and the LX2 – enabling the transfer of large amounts of software-modeled transactions, video streams, or other test stimulus for system validation.

Protobridge AXI

Figure 3: ProtoBridge

MDM Pro features deep trace debugging with cross-triggers for up to eight FPGAs, multi-FPGA signal trace viewing from a single viewing window, 64GB of external trace waveform storage, trace sampling rates up to 125MHz, and supports trigger state machine languages for complex trace captures requirements.

MDM Pro

Figure 4: MDM Pro

S2C’s also offers a rich library of Prototype Ready IP for the LX2 – plug-and-play Daughter Cards – that speeds the creation of the prototyping environment around the FPGA prototype.

Prototype Ready IP s2c fpga

Figure 5: Prototype Ready IP Daughter Cards

Prodigy Logic Matrix LX2 is available now.  For more information, please contact your local S2C sales representative, or visit www.s2ceda.com.

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