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Demonstration of Dose-Driven Photoelectron Spread in EUV Resists

Demonstration of Dose-Driven Photoelectron Spread in EUV Resists
by Fred Chen on 05-08-2022 at 10:00 am

Demonstration of Dose Driven Photoelectron Spread in EUV Resists

As a consequence of having a ~13.5 nm wavelength, EUV photons transfer ~90% of their energy to ionized photoelectrons. Thus, EUV lithography is fundamentally mostly EUV photoelectron lithography. The actual resolution becomes dependent on photoelectron trajectories.

Photoelectron trajectories in EUV lithography were first extensively studied by Kotera et al. [1]. Photoelectrons are preferentially generated along the polarization direction. As EUV light is unpolarized and propagating mostly vertically in the resist, the photoelectron propagation direction tends to be in any random horizontal direction. Thus, the particular direction can be chosen from a uniform random distribution of angles between 0 and 360 degrees. At the same time, the distance traveled can be selected from a random quantile of an exponential distribution [2].

As shown in the figure below, the resulting distribution of distances over which the photoelectrons migrate and deposit their energy is randomly and irregularly shaped. It also depends very much on how many photoelectrons are generated within the same volume of resist, which is proportional to the dose.

EUV photoelectron lateral spread vs. accumulated dose, showing 1X, 2X, 3X, and 4X nominal dose levels. The top and bottom are two separate cases. Initial photoelectron position is (0,0). Nominal 1X dose is 60 mJ/cm2. With an absorption coefficient of 20/um [3], 22% of the light is absorbed in lower half of 40 nm metal-oxide resist, leading to 9 photoelectrons/nm2. Poissonian shot noise is not considered here. Axis labels are in nm.

Increasing the dose very obviously increases the photoelectron spread, effectively increasing the blur. Yet, a higher dose is needed to reduce the impact of Poissonian shot noise, which has not been considered here. The 3-sigma deviation for 9 absorbed photons is 100% [4]! Quadrupling the dose would halve it to 50%. There is therefore an unavoidable resolution-roughness tradeoff in EUV photoresists.

References

[1] M. Kotera et al., “Extreme Ultraviolet Lithography Simulation by Tracing Photoelectron Trajectories in Resist,” Jpn. J. Appl. Phys. 47, 4944 (2008).

[2] https://en.wikipedia.org/wiki/Exponential_distribution

[3] A. Grenville et al., “Integrated Fab Process for Metal Oxide EUV Photoresist,” Proc. SPIE 9425, 94250S (2015).

[4] https://en.wikipedia.org/wiki/Shot_noise

This article first appeared in LinkedIn Pulse: Demonstration of Dose-Driven Photoelectron Spread in EUV Resists 

Also Read:

Adding Random Secondary Electron Generation to Photon Shot Noise: Compounding EUV Stochastic Edge Roughness

Intel and the EUV Shortage

Can Intel Catch TSMC in 2025?


The Jig is Up for Car Data Brokers

The Jig is Up for Car Data Brokers
by Roger C. Lanctot on 05-08-2022 at 6:00 am

John Oliver Car Data Brokers

The same week that John Oliver took on the topic of privacy on his HBO program “Last Week Tonight,” one of the leading automotive data brokers – Otonomo – became the target of a class action lawsuit in California. While Oliver detailed the creepiness of everyday privacy violations on computers, mobile phones, and connected televisions, the lawsuit highlighted the privacy-compromising possibilities of connected cars.

Lawyers from Edelson PC have alleged that Otonomo collects location data on thousands of California residents resulting in a violation of the California Invasion of Privacy Act. The implications are sobering for both car makers and the dozen or more vehicle data brokers that have given form to this new market sector.

Otonomo rose to prominence with a billion-dollar SPAC in 2021. The special purpose acquisition corporation (SPAC) merger in August of last year valued money-losing Otonomo at $1.09B with a stock price of $8.31 a share. The gross proceeds of the SPAC were $255.1M for Otonomo, the stock price of which today stands at less than $2.

Otonomo was not alone in SPAC-ing in 2021. Fellow data broker startup Wejo concluded its own successful SPAC merger following Otonomo’s. Like Otonomo, Wejo’s stock has plunged since going public and the most recent quarterly results – reported March 31 – show an enormous $67.7M net loss with a further $100M+ loss anticipated for 2022.

Enthusiasm for “monetizing” car data was inspired by a notorious 2016 McKinsey report which estimated the value of car data at between $450B and $750B. What many readers of the report ignored was the portion of that forecasted value that was derivative or indirect. These literal interpreters and their car company enablers have sought to directly monetize vehicle data by literally selling it to growing networks of service providers and retailers also seeking to cash in.

The McKinsey report unleashed a gold rush among startups and established players seeking to unlock those billions. Car companies themselves got in on the act with companies such as Volkswagen, Audi, and Stellantis proclaiming that they would soon derive more value and revenue from car data than they would from selling vehicles.

Companies including Caruso and Xapix emerged alongside Wejo and Otonomo. All of these companies began collecting data from a range of sources including direct access to vehicle data from car makers (GM and Volkswagen sharing data with Wejo) as well as data derived from aftermarket devices and connected car smartphone apps.

The dismal reality is now setting in that not only is it difficult to extract value from car data (which often needs to be “cleaned up” and anonymized), it may also be illegal if not done properly. Data monetizers need expertise to extract value from vehicle data and they also need consumer consent.

Most early vehicle data applications derived first and foremost from vehicle tracking – i.e. the basic business of locating vehicles which may be in transit, making deliveries, or stolen. Of late, the emphasis has shifted toward vehicle diagnostics and driver behavior for service scheduling and insurance applications, respectively.

Most rental agreements and new car sales agreements include language regarding customer consent – but consent is often obtained as part of a fairly opaque process. The consumer scans past the small print that gives the dealer or auto maker the right to collect and resell vehicle data. This appears to be the case in the Otonomo class action.

Vice.com reports: “The plaintiff in the case is Saman Mollaei, a citizen of California. The lawsuit does not explain how it came to the conclusion that Otonomo is tracking tens of thousands of people in California.

“Mollaei drives a 2020 BMW X3, and when the vehicle was delivered to him, it contained an electronic device that allowed Otonomo to track its real-time location, according to the lawsuit. Importantly, the lawsuit alleges that Mollaei did not provide consent for this tracking, adding that ‘At no time did Otonomo receive—or even seek—Plaintiff’s consent to track his vehicle’s locations or movements using an electronic tracking device.’

“More broadly, the lawsuit claims that Otonomo ‘never requests (or receives) consent from drivers before tracking them and selling their highly private and valuable GPS location information to its clients.’ The lawsuit says that because Otonomo is ‘secretly’ tracking vehicle locations, it has violated the California Invasion of Privacy Act (CIPA), which bans the use of an ‘electronic tracking device to determine the location or movement of a person’ without consent.”

Otonomo says it protects customer privacy and obtains consent. Vice previously published an account of a 2021 investigation which revealed that data obtained from Otonomo could be used “to find where people likely lived, worked, and where else they drove.”

There is little doubt that vehicle data has value. Whether the value of that data amounts to hundreds of billions of dollars is debatable. What is clear, though, is that the organizations looking to cash in need consumer consent.

The Alliance for Automotive Innovation, representing the interests of foreign and domestic auto makers, has a privacy policy on its Website with two principles:

Participating automakers commit to:

1.     Providing customers with clear, meaningful information about the types of information collected and how it is used

2.   Obtaining affirmative consent before using geolocation, biometric, or driver behavior information for marketing and before sharing such information with unaffiliated third parties for their own use

Andrea Amico, founder of Privacy4Cars, a data privacy advocacy group, noted that the automotive industry continues to fall well short of these objectives. Amico said that auto makers seeking to access vehicle data need to provide:

1.     A clear, prominent notice

2.   A method for the customer to provide affirmative consent

3.   An easy-to-use method for the customer to opt out

4.   A process for managing a change in vehicle ownership

5.   A process for erasing data

6. The one exception might be data related to the operation of a safety or emergency response system – as well as data reporting required by regulatory authorities. Of course, internal use of data by an auto maker is to be distinguished from data used by, sold to, or shared with third parties.

As an example, Aiden is a vehicle data startup focused on the growing number of cars arriving in the market equipped with the Android Automotive operating system. Last week and at the Consumer Electronics Show in January, Aiden demonstrated a first notice of loss (FNOL) car insurance application with an in-dash consumer consent element.

The application provides a complete in-dash display of all data to be shared with the insurance company with the option for the consumer to “Accept,” delay a response: “Later,” or “Reject.” This is a clear and prominent display requiring an affirmative response (which could also be a rejection).

SOURCE: In-dash screen shot of Aiden FNOL consent form.

Current auto maker and, by extension, new car dealer privacy policies are inadequate to fulfill the requirements of prominent notification, affirmative consent, customer control, and ownership transfer. Under current conditions, the Privacy4cars representative suggested that the Otonomo class action is not likely to be the last.

Car makers, rental car companies, and operators of car sharing programs need to review their policies for data management and privacy. We know it isn’t easy to monetize vehicle data – as demonstrated by two money-losing SPACs. Now we know it also requires consent.

Also Read:

ITSA – Not So Intelligent Transportation

OnStar: Getting Connectivity Wrong

Tesla: Canary in the Coal Mine


Podcast EP77: The origins, model and aspirations of EFabless with Mike Wishart and Jeff Dicorpo

Podcast EP77: The origins, model and aspirations of EFabless with Mike Wishart and Jeff Dicorpo
by Daniel Nenni on 05-06-2022 at 10:00 am

Dan and Mike are joined by Mike Wishart, the CEO of EFabless and Jeff Dicorpo, SVP and General Manager. The origins, model, plans and expected impact on innovation by eFabless are all discussed.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


CEO Interviews: Dr Ali El Kaafarani of PQShield

CEO Interviews: Dr Ali El Kaafarani of PQShield
by Daniel Nenni on 05-06-2022 at 6:00 am

Dr Ali El Kaafarani Profile Picture

Dr Ali El Kaafarani is the founder and CEO of PQShield, a British cybersecurity startup specialising in quantum-secure solutions. A University of Oxford spin-out, PQShield is pioneering the commercial roll-out of a new generation of cryptography that’s fit for the quantum challenge, yet integrates with companies’ legacy technology systems to protect them from the biggest threats of today and tomorrow. Dr El Kaafarani is a research fellow at Oxford’s Mathematical Institute and a former engineer at Hewlett-Packard Labs, with over a decade of academic and industrial experience. He is also a leading authority in the cryptography community.

Tell us about PQShield?

PQShield is a cybersecurity company specialising in post-quantum cryptography (PQC). We are the only company that can demonstrate quantum-safe cryptography on chips, in applications, and in the cloud.

Headquartered in the UK and with teams in the US, France, Belgium,the Netherlands, and Japan, our quantum-secure cryptographic solutions work with companies’ legacy systems to protect devices and sensitive data now and for years to come.

Our team has one of the world’s highest concentrations of software and hardware cryptography experts outside academia and the classified sector. PQShield was a leading contributor to the National Institute of Standards and Technology (NIST) post-quantum cryptography standardisation project, and members of the PQShield team have also contributed multiple cryptographic extensions to RISC-V, the open standard instruction set architecture (ISA) that is rapidly gaining traction from proprietary competitors such as ARM and Intel.

What problems/challenges are you solving?

Today, virtually every organisation, government and device in the world relies on public-key cryptography that will be rendered useless by large-scale quantum computers. The vast processing power of these machines will easily solve the mathematical problems underpinning public-key algorithms, making them useless.

Simply put, quantum computers will be able to smash through current protections, leaving data vulnerable. Whether medical records, national intelligence, intellectual property, financial transactions or end-to-end encrypted messaging, the result could be devastating.

Complicating this unprecedented threat is the challenge posed by ‘harvest now, decrypt later’ attacks. Bad actors could steal encrypted data from a business or organisation through a more conventional attack today, and then store this information for when a quantum computer capable of breaking the encryption is built. This threat means that any organisation that wants to secure its data over a longer lifespan must take steps to adopt quantum safe encryption as soon as possible, or risk exposing any current data to a quantum attack. They must also operate under the assumption that any attack in which encrypted data is harvested could present further reputational and regulatory issues in a decade’s time.

What markets does PQShield address today?

We are working with businesses up and down the supply chain to incorporate post-quantum cryptography, across sectors and across geographies.

Specifically, we support businesses who either need to secure data over a long time span or who operate in strategic sectors such as semiconductor, defence, automotive OEM, industrial IoT, and finance.

What are the products PQShield have to offer?

We have a range of post-quantum cryptographic solutions including ready-made and tailored hardware cryptography IPs for low and high-end devices (secure elements, hardware security modules (HSMs), etc.); IoT firmware; public key infrastructure (PKI); server technologies; and advanced end-to-end encrypted messaging platforms.

We have already experienced a surge in demand from different sectors, particularly,  semiconductor and defence, over the last 18 months.

What keeps your customers up at night?

For many, they are still coming to grips with the scale of the quantum threat. They are unaware of where they are exposed and to what extent.

As a result, our first recommendation is to start a comprehensive cryptography audit. In other words, where, why and how are you using cryptography in your organisation? From this point, you can grade your quantum agility – the ability to roll out post-quantum cryptography across your digital infrastructure. With this understanding you can build a comprehensive roadmap to quantum security, factoring in wider business needs and working on realistic timelines.

What makes PQShield unique?

As well as our contributions to the NIST post-quantum cryptography project and having a world-class team of cryptographers and mathematicians, we also have some of the industry’s most advanced engineering expertise. Cybersecurity problems can only be addressed end-to-end, and that’s why at PQShield, we focus on addressing the quantum threat from low level hardware all the way up to advanced protocols.. Our combination of technical expertise with practical engineering experience enables us to help companies protect information from today’s attacks while preparing organisations for the threat landscape of the future.

What added value do you bring to your customers?

We have ensured that we remain an algorithm-agnostic vendor, offering size and performance-optimised implementations of all of NIST’s PQC finalist algorithms, which means that we could support companies in their transition to quantum-readiness even before the NIST standards were announced.

In addition, we have already made a number of strategic partnerships with technology and security consultants to support their customers in their transition to quantum security. We have an expert team who are able to offer unique and bespoke advisory for companies with specific needs.

What’s driving the company’s global expansion/growth?

We have recently had a stimulus from our $20 million Series A funding round which we are already using  to fuel development, hiring and expansion, particularly in the US and Japan.

We’re also seeing huge inbound demand, in part because this is such a critical time for PQC. On the one hand, there’s the pending announcement of new international standards for post-quantum cryptography,and on the other, there’s an increase in the government agencies expressing the urgency of quantum-readiness – whether that’s the NSA in the US, the UK’s GCHQ, or France’s ANSSI.

In January, the White House issued a memorandum on improving national security, outlining the need for quantum resistant protocols on a wide scale. They have advised that within 180 days from publication, all government agencies should implement ‘a timeline to transition these systems to use compliant encryption, to include quantum resistant encryption’. The clock is ticking.

We can see every week that the advances in quantum technology are progressing rapidly, and yet businesses and governments have still not yet fully woken up to the fundamental threat to how we operate digitally. The quantum threat exists today and we must be taking steps to identifying and replacing vulnerable encryption and transitioning towards a quantum secure future.

Also read:

WEBINAR: Secure messaging in a post-quantum world

NIST Standardizes PQShield Algorithms for International Post-Quantum Cryptography

Post-quantum cryptography steps on the field


Efficient Memory BIST Implementation

Efficient Memory BIST Implementation
by Daniel Payne on 05-05-2022 at 10:00 am

Figure 1 min

Test experts use the acronym BIST for Built In Self Test, it’s the test logic added to an IP block that speeds up the task of testing by creating stimulus and then looking at the output results. Memory IP is a popular category for SoC designers, as modern chips include multiple memory blocks for fast, local data and register storage needs. As the number of memory IP blocks increases in a chip, the challenge is how to implement memory BIST for the minimum area, and maximum throughput.  A recent white paper from Harshitha Kodali, Product Engineer at Siemens EDA, focused on this topic, and I’ve learned how a shared bus architecture is the most efficient implementation.

Here’s what a shared bus architecture looks like, where the shared bus is shown in black, physical memories are in teal color, and the physical memories are combined into four logical memories:

Shared Bus Interface

The MBIST logic used to test any of these memories has several components:

Memory BIST shared bus hardware

Engineers insert this DFT logic automatically at the RTL or gate-level, and they define the memories using a Tessent Core Description (TCD) which has details like:

  • Shared bus interface ports
  • Access codes per logical memory
  • Port mappings between logical memories and shared bus interface

Shared bus learning is a methodology to automatically map the physical memory makeup of every logical memory, and verify that the cluster and logical memory library files are proper. Here’s the flow:

Shared bus learning flow

The library validation step ensures that no memory is missed from MBIST testing, port mappings are consistent, and that pipeline stages around the logical memory are consistent with the cluster TCD.

There are five steps to insert the shared bus logic into a design, where ICL is the Instrument Connectivity Language used by a IJTAG flow:

DFT insertion flow

For larger memories the yield can be improved if repairable memories are used, so the Tessent MemoryBIST approach does support this, and inserts the Built-In Repair Analysis (BIRA) plus Built-In Self Repair (BISR) logic. The added BIRA and BISR logic is shown below:

Repairable memory logic

Simple memory instances have a single port for Reading and Writing, however more complex configurations like multi-port and pseudo-vertical stacking are also supported with Tessent MemoryBIST. All of the memory configuration details are defined in the logical memory TCD.

The DFT area overhead can also be optimized if the design has identical memory instances that are not tested concurrently, as the memory interface and virtual memory will be reused.

Summary

Memory BIST with many IP instances can be efficiently implemented with a shared bus test using Tessent MemoryBIST.  There’s quite a bit of flexibility in the DFT automation approach offered by Siemens EDA to handle physical memories, logical memories, memory library mapping and validation.

The complete White Paper is available to view online, with a simple registration step, or there’s a recorded webinar online to view.

Related Blogs


Design IP Sales Grew 19.4% in 2021, confirm 2016-2021 CAGR of 9.8%

Design IP Sales Grew 19.4% in 2021, confirm 2016-2021 CAGR of 9.8%
by Eric Esteve on 05-05-2022 at 6:00 am

Table IP 2020 2021 1

Design IP Sales reached $5.45B in 2021, or 19.4% YoY after 16% in 2020, on-sync with semiconductor growth of 26.2% in 2021 according to WSTS. IPnest has released the “Design IP Report” in May 2022, ranking IP vendors by category (CPU, DSP, GPU & ISP, Wired Interface, SRAM Memory Compiler, Flash Memory Compiler, Library and I/O, AMS, Wireless Interface, Infrastructure and Misc. Digital) and by nature (License and Royalty).

The main trends shaking the Design IP in 2021 are very positive for most of the IP vendors, especially for Synopsys growing by 21.7%, more than the market, as well as Imagination Technologies (IMG) by 43.4% and Flash memory compiler vendors (SST, eMemory Technology) and Alphawave with more than 100% growth.

Synopsys and Alphawave growth confirm the importance of the wired interface IP market (with 22.7% growth for the category) aligned with the data-centric application, hyperscalar, datacenter, networking or IA. But the good performance of ARM and IMG proves the come back of the smartphone industry and the emergence of automotive as a growth vector.

Looking at the 2016-2021 IP market evolution can bring interesting information about the main trends. The global IP market has grown by 59.3% when Top 3 vendors have seen unequal growth. The #1 ARM grew by 33.7% when the #2 Synopsys grew by 140.9% and Cadence (#3) by 167.2%. Market share information is even more significant. ARM moved from 48.1% in 2016 to 40.4% in 2021 while Synopsys enjoyed a move from 13.1% to 19.7% (or a gain of 50% of market share from 2016 to 2021!) and Cadence is progressing from 3.4% to 5.8%.

This can be synthetized with the comparison of 2016 to 2021 CAGR:

The strong information is that the Design IP market has enjoyed almost 10% CAGR for 2016-2021! It’s also noticeable that Synopsys with 19.2% CAGR has grown more than three times compared with ARM (6% CAGR).

IPnest has also calculated the IP vendors ranking by License and royalty IP revenues:

Synopsys is the clear #1 winner by IP license revenues with 31.2% market share in 2021, while ARM is #2 with 25.6%. Alphawave, created in 2017, is now ranked #4 just behind Cadence, showing how high performance SerDes IP is essential for modern data-centric application (Alphawave is leader for PAM4 112G SerDes available in 7nm, 5nm and 3nm from various foundries, TSMC, Samsung and Intel-IFS).

Semiwiki readers shouldn’t be surprised, as I had predicted importance of SerDes IP in a blog written in 2012 “Such a small piece of Silicon, so strategic PHY IP” http://www.semiwiki.com/forum/content/1241-such-small-piece-silicon-so-strategic-phy-ip.html

In fact, Synopsys good performance is partly related to their strong focus on the wired interface category, where they enjoy 55.6% of 1.3B market, and high performance SerDes is the main pilar of the interconnect market. Synopsys has adopted a “One-Stop-Shop” strategy, supporting almost all protocols (USB, PCIe, Ethernet, SATA, HDMI, MIPI, DDR Memory Controller) and enjoying leading market share in every protocol.

Alphawave is complementary in the sense that their strategy is more “Stop-For-Top”, restricting their support to the most advanced products on the leading-edge technology nodes. If we look at 2021 Design IP results, both can be successful, following a different strategy and market positioning.

The 2021 ranking for Royalty shows ARM’s dominance with 60.8% market share, not a surprise if we consider their customer installed base and their strong position in the smartphone industry. More surprising is the come back of SST and Imagination Technologies (IMG) resp. #2 and #3 in this Top 5.

SST is benefiting from the microcontroller upturn as they equipped the majority of microcontroller products sold. IMG has been able to overcome the air pocket generated by Apple a few years ago, and re-position as a modern GPU provider in various segments on top of smartphone like automotive entertainment, Smart TV or Tablet.

With 19.4% YoY growth in 2021, the Design IP industry is simply confirming how incredibly healthy this niche is within the semiconductor market and the past 2016 to 2021 CAGR of 9.8% is a good metric! IPnest has also run a 5-year forecast (not yet published) for Design IP, to weight $11B in 2026 and predict a future CAGR (2021 to 2026) of 15%. Optimistic? This year-to-year 2021 growth is on-line with this prediction…

Eric Esteve from IPnest

To buy this report, or just discuss about IP, contact Eric Esteve (eric.esteve@ip-nest.com)

Also read:

Chiplet: Are You Ready For Next Semiconductor Revolution?

IPnest Forecast Interface IP Category Growth to $2.5B in 2025

Design IP Sales Grew 16.7% in 2020, Best Growth Rate Ever!


Podcast EP76: Geopolitical Forces on Semis, the Past, Present and Future with Terry Daly

Podcast EP76: Geopolitical Forces on Semis, the Past, Present and Future with Terry Daly
by Daniel Nenni on 05-04-2022 at 10:00 am

Dan is joined by Terry Daly, a 35-year veteran of the semiconductor industry, former senior VP at GLOBALFOUNDRIES and an executive at IBM Microelectronics. Terry is currently an independent consultant, and also a Senior Fellow at the Council on Emerging Market Enterprises at The Fletcher School of Law & Diplomacy at Tufts University.

Dan and Terry discuss the various sanctions, subsidies, competition and legislation associated with the semiconductor industry, with a view of how we got here and where it all may take us.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual


Tensilica Edge Advances at Linley

Tensilica Edge Advances at Linley
by Bernard Murphy on 05-04-2022 at 6:00 am

NNE graphic min

The Linley spring conference this year had a significant focus on AI at the edge, with all that implies. Low power/energy is a key consideration, though increasing performance demands for some applications are making this more challenging. David Bell (Product Marketing at Tensilica, Cadence) presented the Tensilica NNE110 engine to boost DSP-based AI, using a couple of smart speaker applications to illustrate its capabilities. Amid a firehose of imaging AI in the media, I for one am always happy to hear more about voice AI. The day when voice banishes keyboards can’t come soon enough for me 😎 These Tensilica Edge advances also support vision applications naturally.

The Need

DSPs are strong platforms for ML processing since ML needs have much in common with signal processing. Support for parallelism and accelerated MAC operations has been essential in measuring, filtering and compressing analog signals for many decades. The jump to ML applications is obvious. As those algorithms rapidly evolve, DSP architectures are also evolving for more parallelism, more MACs and more emphasis on keeping big data sets (weights, images, etc) on-chip for as long as possible to limit latencies and power.

Another area of evolution is in specialized accelerators to augment the DSP for specialized functions with even lower latency and power. In voice-based applications, two very important examples are noise suppression and trigger word detection. In noise suppression, intelligent filtering can now do better than conventional active noise filtering. Trigger word detection must be always-on, running at ultra-low power to allow the rest of the system to remain off until needed. Recognizing trigger words requires ML, at ultra-low power.

Meeting these needs with NNE110

A now popular method for de-noising is based on an LSTM network trained to separate speech from environmental noise. This allows adapting across a wide variety of environment possibilities. Profiling reveals that 77% of these operations running on pure DSP implementation are matrix and vector operations, and about half the remaining operations are in activation functions such as sigmoid or tanh. These are obvious candidates to run on the accelerator. Comparing between pure DSP and DSP+NNE implementations, both latency and power improve by over 3X. For a different de-noising algorithm , latency and power reduce even more dramatically, by 12X and 15X respectively. This is for a CNN  based on U-NET, here adapted from a different domain.

Implementation

The NNE accelerator looks like it slips in very cleanly to the standard Tensilica XAF flow. In mapping instructions from TensorFlow Lite for Microcontrollers, standard Tensilica HiFi options are reference ops and HiFi optimized ops. NNE ops are just another option connected through a driver to the accelerator. In development, supported operations simply map to the accelerator rather than one of the other classes of ops.

David pointed out that multiple applications can benefit from this fast and very low-power always-on extension. This is in the visual domain as well as in voice recognition. Obvious candidates include trigger word recognition, visual wake words, gesture detection and more.

If you want to learn more, you probably had to be registered to the Linley conference to get the slides, however Cadence has a web page on NNE. Also you can learn more about the LSTM algorithm HERE and the U-NET algorithm HERE.

Also read:

ML-Based Coverage Refinement. Innovation in Verification

Cadence and DesignCon – Workflows and SI/PI Analysis

Symbolic Trojan Detection. Innovation in Verification

 


Bigger, Faster and Better AI: Synopsys NPUs

Bigger, Faster and Better AI: Synopsys NPUs
by Kalar Rajendiran on 05-03-2022 at 10:00 am

ARC NPX6 440 TOPS

AI-based applications are fast advancing with evolving neural network (NN) models, pushing aggressive performance envelopes. Just a few years ago, performance requirements of NN driven applications were at 1 TOPS and less. Current and future applications in the areas of augmented reality (AR), surveillance, high-end smartphones, ADAS vision/LiDAR/RADAR, high end gaming and more are calling for 50 TOPS to 1000+ TOPS. This trend is leading to development of neural processor units (NPUs) to handle this demanding requirement.

Pierre Paulin, Director of R&D, Embedded Vision at Synopsys gave a talk on NPUs at the Linley Spring Conference April 2022. His presentation was titled “Bigger, Faster and Better AI: Synopsys NPUs” and covered their recently announced ARC NPX6 and ARC NPX6FS processors. This post is a synopsis of the salient points from his talk.

Embedded Neural Network Trends

Four factors contribute to the increasing levels of performance requirements of artificial intelligence (AI) applications.

  • AI research is evolving and new neural network models are emerging. Solutions must be able to handle models such as the AlexNet from 2012 as well as the latest models such as the transformer and recommender graphs.
  • With the automotive market being a big adopter of AI, the applications need to meet functional safety requirements standards. This market requires mature and stable solutions.
  • Applications are leveraging higher definition sensors, multiple camera arrays and more complex algorithms. This calls for parallel processing of data from multiple types of sensors.
  • All of the above push more requirements on to the SoCs implementing and supporting the AI applications. The hardware and software solutions should enable quicker and quicker time to market.

Synopsys’ New Neural Processing Units (NPUs)

Synopsys recently introduced their new NPX series of NPUs to deliver performance, flexibility and efficiency demanded by the latest NN trends.

The NPU core of the NPX6 offering is based on a scalable architecture with 4K MACs building blocks. A single NPU instance can be built from 1 to 24 NPU cores. A multi-NPU configuration can include up to 8 NPU instances. Synopsys also offers NPX6FS to support the automotive market. Refer to the Figures below for corresponding block diagrams.

The key building block within the NPU core is the Convolution Accelerator. Synopsys’ main focus was on MAC utilization for handling the most modern graphs such as the EfficientNet. The NPX6/NPX6FS contain a generic tensor accelerator to handle the non-convolution parts and fully supports the Tensor Operator Set Architecture (TOSA).

A high bandwidth, low latency interconnect is included within the NPU core and is coupled with high-bandwidth L1 and L2 memories. The NPX6 also includes an intelligent broadcast feature which works as follows. Anytime a feature map or coefficient is read from external memory, it is read only once and reused as much as possible within the core. The data is broadcast only when used by more than one core.

Of course, the hardware is only half the story. The other half is software and Synopsys has been working on the entire effort for many years to deliver a solution that is fully automatic. Some of the key features/functionality are mentioned below.

Flexibility

With every new NN model comes a new activation function. The NPX6/NPX6FS cores support all activation functions (old, new and ones yet to come) using a programmable lookup table approach.

Enhanced datatype support

Though the industry is moving toward 8 bit datatype support, there are still cases where a mix of datatypes is appropriate. Synopsys provides a tool that automatically explores the hybrid versions of a couple of layers in 16 bit and all other layers in 8 bit. The NPX6 supports FP16 and BF16 (as options) with very low overhead. Customers are taking this option to quickly move from a GPU oriented, power hungry solution to an embedded, low power, small form factor solution.

Latency reduction

Instead of pipelining, the NPX architecture takes an approach of parallelizing a convolutional layer on multiple cores to deliver both higher throughput and lower latency.

Power Efficiency

The NPX6 is able to achieve 30 TOPS/W in 5nm, which is an order of magnitude better than many solutions out there today.

Bandwidth Reduction

With a machine running at over 100 TOPS, the NPX6 is able to handle the bandwidth requirement with a LPDDR4/LPDDR5 class of memory interface.

Benchmark Results

Refer to Figure below for performance benchmark results when comparing Frames per second per Watt as the metric.

On-Demand Access to Pierre’s entire talk and presentation

You can listen to Pierre’s talk from here, under “Keynote and Session 1.”  You will find his presentation slides here, under “Day 1 – Keynote – AM Sessions.”

Also read:

The Path Towards Automation of Analog Design

Design to Layout Collaboration Mixed Signal

Synopsys Tutorial on Dependable System Design

 

 


Future.HPC is Coming!

Future.HPC is Coming!
by Daniel Nenni on 05-03-2022 at 6:00 am

HPC Image Altair SemiWiki

According to the experts, the semiconductor industry is poised for a decade of growth and is projected to become a trillion dollar industry by 2030. In 2021 the semiconductor industry finally hit $600B so $1T by 2030 seems like a big ask, but not really if you look at the indicators inside the semiconductor ecosystem. Foundries, EDA, IP, and other ecosystem markers grew at record levels in 2021. The $1T question is: What will be the next big driver in the next decade for semiconductors?

The answer of course is high performance computing (HPC) and if you want to learn  more about HPC market segments Argonne National Laboratory, 3M, and Google are a great place to start:

Future.HPC Virtual Event

Register Here

Compute Intelligence for Breakthrough Results

Altair’s flagship high-performance computing event looks at outstanding HPC-driven end results customers have realized in the last year. HPC professionals from across the globe will share how they empower their organizations to turn CPUs and GPUs into groundbreaking medical research, faster planes and automobiles, smaller chips, smarter financial models, and so much more.

Featuring a mix of leadership presentations, panel discussions, breakout sessions, and networking opportunities, attendees can connect with and learn from fellow designers, engineers, IT specialists, and data scientists on the latest technology topics influencing every industry and the world around us.

All presentations will have live audio translations into French, Spanish, German, Italian, and Portuguese.  The event will be presented in two time zones – CEST (Europe & APAC) and EDT (AMER).

Join experts from Argonne National Laboratory, 3M, Google, WIRED Editor-in-Chief Greg Williams, and many more, for leadership presentations, roundtables, breakout sessions, and networking opportunities. Whether you’re an HPC pro or an end-user who prefers to keep the complexity “under the hood,” Future.HPC is the place to connect virtually with designers, engineers, IT specialists, and data scientists accelerating innovation timelines in your industry.

Day One Tuesday May 17, 2022

10:00 AM (Paris); 1:30 PM (India); 4:00 PM (Shanghai/Kuala Lumpur)
11:00 AM (New York); 8:00 AM (San Francisco); 10:00 AM (Mexico City); 12:00 PM (Sao Paulo)

Welcome and Introduction

Dr. Rosemary Francis, Chief Scientist, Altair
Rick Watkins, Senior Director Cloud Computing, Altair

Altair Keynote

James R. Scapa, Founder, Chairman, & CEO, Altair,
Joe Sorovetz, SVP Enterprise Solutions, Altair

Harnessing the Great Acceleration

Greg Williams, Editor-in-Chief, WIRED Magazine

The next big technology trends that will be driven by supercomputing.

3M: Accelerating Cloud Adoption for HPC Workloads with Altair PBS Professional and Altair Control

Gabe Turner, HPC Solutions Architect, 3M

With approximately 60,000 products spanning four business groups, 3M is constantly improving products to fit the needs of its customers. Modeling and simulation touch many stages of the product development process at 3M and high-performance computing is critical to accommodating such computationally intensive workloads. 3M has been using Altair PBS Professional for many years to great success, and in 2018 became an early adopter of Altair Control and its cloud bursting capabilities for HPC.

Google: Feature Partner Presentation

Dr. William (Bill) Magro, Chief Technologist, High-Performance Computing , Google

Building the Future of HPC Workload Management at ANL

William Allcock, ALCF Advanced Integration Group, Argonne National Laboratory

As Argonne National Laboratory prepares to support researchers tackling critical problems on its Polaris supercomputer and eventually its Exascale system, Aurora, William (Bill) Allcock, Manager, ALCF Advanced Integration Group, outlines the critical role of workload management in advancing what’s possible with HPC. He will share how his team’s initial exploration of open-source workload management technology led to their adoption of Altair’s commercial solution, PBS Professional, in 2021, and to a partnership between HPC experts at ANL and Altair that will …

HPC at Punch Torino

Mauro Bighi, CIO PUNCH Group

Panel Discussion on High-performance Computing: Decades of Technological Advancement Give Drastically New Meaning to “HPC”

Dr. Bill Nitzberg, Chief Engineer – HPC, Altair
Fritz Ferstl, SVP Software Development, Altair
Stuart Taylor, Director Software Development, Altair

At this moment, Altair has the largest brain trust of HPC expertise in the world. Join the experts who have shepherded technology as original as PBS, Sun Grid Engine and Runtime Design Automation into today’s high stakes commercial HPC space. They’ll discuss the decades of advancement, development and acquisition that went into assembling the most comprehensive HPC optimization portfolio on the market, preparing us for an all new definition of “high performance computing.”

Day Two Wednesday May 18, 2022

10:00 AM (Paris); 1:30 PM (India); 4:00 PM (Shanghai/Kuala Lumpur)
11:00 AM (New York); 8:00 AM (San Francisco); 10:00 AM (Mexico City); 12:00 PM (Sao Paulo)
Welcome and IntroductionDr. Rosemary Francis, Chief Scientist, AltairA Cloud for Every Workload: Which Model is Right for You?

Rick Watkins, Senior Director Cloud Computing, Altair

As the leading provider of workload management and compute optimization technology for three decades, Altair has helped enterprise computing customers at the cutting edge of HPC move critical workloads to the cloud. Now, we’re helping thousands of simulation software end users enticed by the promise of increasing exploration potential with “infinite” scalability do the same. Whether you’re an HPC expert looking for tools to tune and optimize or an end user looking to boost productivity without IT complexity, join cloud.

Parallel Track – Cloud for End Users: Turbocharge Engineering Productivity, No IT Expertise Required

Raghvendra Srivastava, Product Manager, Altair

HPC and cloud accessibility make it possible to scale exploration exponentially, but the key to breakthrough results is ensuring time spent interfacing with IT doesn’t scale accordingly. In this breakout session just for simulation application end users, attendees will see how the most competitive teams access their software, their data, and powerful HPC resources to turbocharge productivity from anywhere in the world. From launching software on any device and accelerating jobs with on-demand solving power to seamlessly visualizing and sharing.

Parallel Track – Cloud for HPC Pros: Expand HPC Infrastructure On-demand with Cost-effective, Multi-cloud Scaling

Ian Littlewood, Product Manager Enterprise Computing, Altair

Beyond empowering your team with flexible compute resources to scale productivity, cloud bursting technology provides tunning and automation opportunities that make real impact on the metrics that matter most to your organization. Join this breakout session for HPC stakeholders to see how to manage, optimize and forecast compute resources, bursting to and between your on-prem resources and Oracle Cloud Infrastructure, Google Cloud Platform, Microsoft Azure, and Amazon Web Services (AWS). “It just works” may be the magic words for end.

Join us for our flagship HPC event for 2022!

Register Now to Receive Agenda Updates

 

About Altair
Altair is a global leader in computational science and artificial intelligence (AI) that provides software and cloud solutions in simulation, high-performance computing (HPC), data analytics, and AI. Altair enables organizations across all industries to compete more effectively and drive smarter decisions in an increasingly connected world – all while creating a greener, more sustainable future. For more information, visit https://www.altair.com/.

Also Read:

Six Essential Steps For Optimizing EDA Productivity

Latest Updates to Altair Accelerator, the Industry’s Fastest Enterprise Job Scheduler

Chip Design in the Cloud – Annapurna Labs and Altair