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Methods for Current Density and Point-to-point Resistance Calculations

Methods for Current Density and Point-to-point Resistance Calculations
by Daniel Payne on 05-26-2022 at 10:00 am
Categories: EDA, Siemens EDA
2 Comments

ESD path min

IC reliability is an issue that circuit design engineers and reliability engineers are concerned about, because physical effects like high Current Density (CD) in interconnect layers, or high point-to-point (P2P) resistance on device interconnect can impact reliability, timing or Electrostatic Discharge (ESD) robustness. Common approaches for these calculations include device-based or cell-based checks, and now there are coordinate-based checks to consider using.

ESD Verification

During ESD verification both P2P and CD checking are used to determine if each ESD discharge path is reliable. In the figure below the ESD paths are shown along the gold-color lines, starting at an input pad, passing through power-clamping devices, then ending up a power or ground pad. The design goal is to keep the surge current away from the devices in blue.

To mitigate ESD failures, a layout designer keeps the resistance along the ESD discharge paths low.

ESD protection paths

Device-based Checks

An EDA tool like Calibre PERC from Siemens EDA can run a device-based P2P check on ESD paths in three steps:

  • Extract a layout netlist
  • Traverse and find ESD devices, power clamping devices
  • Extract and simulate resistance network, measure ESD effectiveness

Your foundry would supply a Calibre PERC rule deck for this ESD analysis to be run, but it’s possible that the PERC rule decks don’t cover all EDS devices or paths. Your company may want to develop custom PERC rule decks for unique ESD structures being used. There’s a learning curve to becoming proficient at writing Calibre PERC rule decks, so creating and verifying custom rule decks will cost you both time and engineering talent.

Cell-based Checks

With cell-based checks you are not considering the details of ESD devices and circuits, rather just the cell names and port names will specify your ESD cells. The upside of using a cell-based check is that run times are much quicker, as the device extraction is disabled during the LVS layout extraction step. This second figure shows the cell-based verification approach:

Cell-based verification

Your Calibre PERC rule deck still has cell names and pins defined, however the downside is that the accuracy of results will be less than that of device-based checks.

Coordinate-based Checks

A design or layout engineer will want to calculate P2P resistance between two coordinate points of a net in the IC layout, before the full-chip verification has been run. When a new IP cell is adding to a chip layout, the team needs to know that power and ground connections are solid. There may also be special nets that require identical lengths between cells.

With coordinate-based checks for layout verification, there is no requirement to write a Calibre PERC rule deck defining devices or cells, so it’s a quicker and easier method to run than P2P and Current Density checks. You do need to define some coordinates for start and end location along a net, along with a layer name, also called probe points. LVS device extraction can be skipped in coordinate-based checks, producing P2P and CD results quickly.

Your probe mapping file is a simple ASCII format, easy to create from a cell’s text file, and the cell coordinates in the top cell. Results from a coordinate-based P2P check are shown next:

P2P check results, Calibre RVE results viewer

Summary

There are three possible methods for  P2P and current density checks when using the Calibre PERC tool:

  • Device-based: most accurate, requires rule deck knowledge, slowest run times
  • Cell-based: less-complex rule decks, fast run times
  • Coordinate-based:  no changes to rule deck, fast run times

Familiarity with the rule deck language is required when using the device-based method, and with advanced nodes an ESD MOS device can have thousands of fingers, slowing down the P2P and Current Density calculations.

The second method introduced, cell-based checks is quick to start using, has an easier rule deck, and enjoys faster run times than device-based checks. So you can always trade off speed and accuracy of results.

The final method of coordinate-based checks has minimal rule deck changes to get started, and the results are easy to debug with RVE, ideal to use for quick layout check when in the initial stage of designing and verifying an SoC.

Read the full nine page White Paper from Siemens EDA here.

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Very Short Reach (VSR) Connectivity for Optical Modules

Very Short Reach (VSR) Connectivity for Optical Modules
by Kalar Rajendiran on 05-26-2022 at 6:00 am
Categories: EDA, IP, Synopsys

Synopsys 112G Ethernet PHY IP for VSR

Bandwidth, latency, power and reach are always the key points of focus when it comes to connectivity. As the demand for more data and higher bandwidth connectivity continue, power management is gaining a lot of attention. There is renewed interest in pursuing silicon photonics to address many of these challenges. There are many other drivers as well behind the push for a broader adoption of silicon photonics. From an implementation perspective, co-packaged optics is going to play a catalyzing role. Co-packaged optics means bringing the optics (which is typically in a face plate) very close to the SoC. Many players within the ecosystem are working together to make co-packaged optics technology a mainstream reality. But it will be some time before that broad adoption happens. Until then, pluggable optical module is the way the industry is serving the optical connectivity requirements.

Manmeet Walia, Director, Product Marketing for high-speed SerDes IP products at Synopsys gave a talk at IP-SoC Silicon Valley 2022 last month. His presentation focused on opportunities for very short reach (VSR) 112G PHY for bringing optical connectivity deeper into the data centers. He discusses trends that are driving this transformation, and presents a solution to overcome the reach constrains of copper modules. This post is a synthesis of his talk. You can download his presentation slides from here.

Trends pushing optics deeper into data centers

Explosion of intra-data center traffic

We are all aware of data explosion, driven by more users, more devices per user, and more bandwidth needed per device. What many may not be aware is that the growth in data traffic within a data center is 5X that of the total internet traffic. And this is growing at a 30% CAGR [Source: Cisco Global Cloud Index 2021]. The processing of this data is getting complex. Even a search query could lead to lot of computation and machine to machine communication/traffic within the data center. This generates a lot of intra-data center traffic that call for wider data pipes and faster processing at very low latency. This in turn is pulling more optics connectivity within the data center than traditional copper connectivity.

Flattening of the networks for low latency

As each switch adds 500ns of latency, a data center architecture is limited to no more than three layers of switches. While the top of rack (TOR) switches are mostly copper, the other two layers are heavily dominated by optics. Due to growing number of servers in the data center and wider data pipes between them, the pressure is on the switches to increase throughput 2X every two years.

Aggregation of Homogeneous Resources

Data centers used to be built with hyperconverged servers where storage, compute and networking were rolled into one box. But that is changing. The new trend is called Aggregation of Homogeneous Resources, aka Server Disaggregation. This concept is the polar opposite of hyperconverged servers. The different functions are separated but connected optically with low latency and high bandwidth. When a workload needs a certain amount of storage and compute, that is exactly what is tapped and connected optically.

Reach constrains of pluggable copper modules

Pluggable copper modules are the reality today but they introduce power issues. The signal from the host SoC is driven through PCB trace and then a retimer inside active pluggable modules, followed by a  2-5 meter copper cable to the other pluggable copper module  in a different rack unit . The high-end, expensive material in the PCB trace reduce signal losses, but increases the total cost of server chassis. Rack unit to rack unit connectivity is achieved by low-loss cable such as 24 AWG which is thick and takes a lot of space. When 100K servers (typical in a data center) are inter-operating over PVT, things inherently breakdown due to over-heating. To minimize this, expensive cooling system is required, which again adds to the datacenter cost.

These issues can be circumvented by using low-power SerDes in the host SoC and as retimers in active copper cables.

Synopsys’ 112G Ethernet PHY IP for VSR

A VSR PHY approach for the pluggable optical module market is an attractive solution until the industry predominantly shifts to a co-packaged optics solution some years from now. Optical modules can be broadly classified into two categories. The ones based on Intensity Modulation Direct Detect (IMDD) lasers support up to 40Km reach. The ones based on Coherent lasers are for distances up to 120Km. Synopsys’ PHY IP is for optical modules supporting IMDD as well as coherent modules (as host side interface).

Synopsys provides a complete solution with lowest power, area and latency to make it easy for customers to integrate, validate and go to production. Its floorplan mockup, signal and power integrity tools and system analysis tools provide a comprehensive platform to solve the multi-dimensional challenge of die, package, channel and connector. The Synopsys’ 112G Ethernet PHY IP for  VSR is emerging as an ideal solution for 800G optical modules.

Also Read:

Bigger, Faster and Better AI: Synopsys NPUs

The Path Towards Automation of Analog Design

Design to Layout Collaboration Mixed Signal

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[WEBINAR] Secure your devices with PUF plus hardware root-of-trust

[WEBINAR] Secure your devices with PUF plus hardware root-of-trust
by Don Dingee on 05-25-2022 at 10:00 am
Categories: Events, Intrinsic ID, IP, Rambus

NVM secret key storage problems

It’s a hostile world we live in, and cybersecurity of connected devices is a big concern. Attacks are rising rapidly, and vulnerabilities get exploited immediately. Supply chains are complex. Regulations are proliferating. Secrets don’t stay secrets for long – in fact, the only secret in a system with open-source algorithms may be the secret key. What if the root secrets were never stored in a device? Hiding keys with a physically unclonable function (PUF) plus a hardware root-of-trust makes this possible – the subject of a recent webinar from Intrinsic ID and Rambus.

Defeating prying eyes with sophisticated tools

It might seem secure to embed a root secret in a chip, using non-volatile memory (NVM). It’s an improvement over the old school methods of jumpers and dip switches. Putting it under the chip lid makes it harder for anyone to change it from the outside. Extra mask steps add processing and test time, and there may redundancy needs. Most process questions are solvable, although NVM is running into difficulty at advanced process nodes.

But a bigger issue is times have changed. Cracking a device key can lead to huge rewards. Physical attackers are no longer armed with just soldering irons, diagonal cutters, and magnifying glasses. X-ray, ion beams, lasers, and other scanning technology can see chip features, revealing a key stored in NVM. Side channel attacks monitoring tiny power supply fluctuations can uncover data patterns transmitted within a chip.

The bottom line is if the secret key is stored somewhere, there are ways to see it. Making the key harder to get may deter the drive-by amateur, but not the well-funded professional hacker with time and the right equipment. If the key can’t be stored, and it can’t be transmitted, how can a device get it?

Entropy plus tamper-resistance for the win

Out of chaos comes order. PUFs put entropy to good use. Anything that varies on chip – such as nanoscale differences in transistors and parasitics – can be an entropy source. For example, a bi-stable cell with cross-coupled transistors is an SRAM cell. In theory, its power up is random, but when fabricated, a given SRAM cell powers up quite repeatably in one of the two states. A sea of these entropy-driven cells creates a repeatable power-on pattern unique to each chip, like a fingerprint. Those prying eyes with sophisticated tools can see a PUF’s structure, but that’s all. The PUF output doesn’t exist in the off state and is tough to predict in the on state. Cloning the structure results in a different output pattern.

Next comes a NIST-certified key derivation function (KDF). The PUF output is essentially a pseudo-random passphrase. Adding encrypted “helper data” usually from NVM that error corrects for noisy bits between power ups, the KDF algorithm derives a reliable and truly random secret key whenever it is needed. Most attacks go after either the NVM value, which doesn’t reveal the PUF output, or the circuit computing the KDF.

This is where a hardware root-of-trust comes in, a tamper-resistant engine securely processing the PUF output. In a finishing touch of synergy, the hardware root-of-trust cooperates in creating the helper data stored in NVM, adding a layer to security. Effectively, this extends the unclonable nature of a PUF to an entire SoC. Here’s one of the final quotes in the webinar:

“Even a perfectly cloned SoC cannot perfectly clone the PUF’s transformation function.”

Readers may have already seen this technology in action, if one has ever tried to stuff a counterfeit printer ink cartridge into a printer and found it doesn’t work. We’ve simplified this discussion, and the details are interesting. Want to see more about how a PUF plus a hardware root-of-trust work in this presentation from experts Dr. Roel Maes of Intrinsic ID and Scott Best of Rambus? To view this archived webinar, please visit:

Secure Your Devices with PUF Plus Hardware Root of Trust

Also read:

WEBINAR: How to add a NIST-Certified Random Number Generator to any IoT device?

Enlisting Entropy to Generate Secure SoC Root Keys

Using PUFs for Random Number Generation

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Refined Fault Localization through Learning. Innovation in Verification

Refined Fault Localization through Learning. Innovation in Verification
by Bernard Murphy on 05-25-2022 at 6:00 am
Categories: AI, Cadence, EDA

Innovation New

This is another look at refining the accuracy of fault localization. Once a bug has been detected, such techniques aim to pin down the most likely code locations for a root cause. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.

The Innovation

This month’s pick is DeepFL: Integrating Multiple Fault Diagnosis Dimensions for Deep Fault Localization. The paper published in the 2019 ACM International Symposium on Software Testing and Analysis. The authors are from UT Dallas and the Southern University of Science and Technology, China.

This is an active area of research in software development. The authors build on the widely adopted technique of spectrum-based fault localization (SBFL). Failures and passes by test are correlated with coverage statistics by code “element”. An element could be a method, a statement, or other component recognized in coverage. Elements which correlate with failures are considered suspicious and can be ranked by strength of correlation. The method is intuitively reasonable though is susceptible to false negatives and positives.

DeepFL uses learning based on a variety of features to refine localization. Methods used include SBFL, mutation-based testing (MBFL), code complexity and textual similarity comparisons between code elements and tests. In this last case, intuition is that related text in an element and a test may suggest a closer relationship. The method shows a significant improvement in correct localization over SBFL alone. Further the method shows promising value between projects, so that learning on one project can benefit others.

Paul’s view

I really appreciate the detail in this paper. It serves as a great literature survey, providing extensive citations on all the work in the ML and software debug communities to apply deep learning to fault localization. I can see why this paper is itself so heavily cited!

The key contribution is a new kind of neural network topology that, for 77% of the bugs in the Defects4J benchmark, ranks the Java class method containing the bug as one of the top 5 most suspicious looking methods for that bug. This compares to 71% from prior work, a significant improvement.

The authors’ neural network topology is based on the observation that different suspiciousness features (code coverage based, mutation based, code complexity based) are best processed first by their own independent hidden network layer, before combining into a final output function. Using a traditional topology, where every node in the hidden layer is a flat convolution of all suspiciousness features, is less effective.

I couldn’t help but notice that keeping a traditional topology and just adding a second hidden layer also improved the results significantly – not to the same level as the authors’ feature-grouped topology, but close. I wonder if added a third hidden layer with a traditional topology would have further narrowed the gap?

Overall, this is great paper, well written, with clear results and a clear contribution on an important topic. It is definitely applicable to chip verification as well as software verification. If anything, chip verification could benefit more since RTL code coverage is more sophisticated than software code coverage, for example in expression coverage.

Raúl’s view

This is a nice follow-on to earlier reviews on using ML to increase test coverage, predict test coverage and for power estimation. These authors use ML for fault localization in SW as an extension of learning-to-rank fault localization. The latter uses multiple suspiciousness values as learning features for supervised machine learning. The paper has 95 citations.

DeepFL uses these dimensions in suspiciousness ranking: SBFL as statistical analysis on the coverage data of failed/passed tests with 34 suspiciousness values for code elements; MBFL uses mutants (140 variants) to check the impact of code elements on test outcomes for precise fault localization; fault-proneness-based features (e.g., code complexity, 37 of these); finally, 15 textual similarity-based features from the information retrieval area. All of these they use to drive multiple deep learning models.

The authors run experiments on the Defects4J benchmark with 395 known bugs, widely used in software testing research. They compare DeepFL to SBFL/MBFL and to various learning-to-rank approaches. They also look at how often the bug location ranked as top probability, or in the Top-3 and Top-5. The authors’ method outperforms other methods within a project and between projects.

They note that the biggest contributor to performance is the MBFL technique. In comparing runtime to a learn-to-rank approach their method takes ~10X to train but is up to 1000X faster in test (runtimes in the range of .04s – 400s).

A very interesting part of their result analysis clarifies how DeepFL models perform for fault localization and whether deep learning for fault localization is necessary at all. Even though the authors conclude that “MLPDFL can significantly outperform LIBSVM” (Support Vector Machines have just one layer), the difference in Top-5 is just 309 vs. 299, a comparatively small gain.

I wish they had written more about cross-project prediction and had compared runtimes to traditional methods. Still, this is a very nice paper showing a SW debugging technique which seems applicable to RTL and higher level HW descriptions and once again highlights an application of ML to EDA.

My view

There are several interesting papers in this area, some experimenting primarily with features used in the learning method. Some look at most recent code changes for example. Some also play with the ML approach (eg graph-based methods). Each shows incremental improvement in localization accuracy. This domain feels to me like a rich vein to mine for further improvements.

Also read:

224G Serial Links are Next

Tensilica Edge Advances at Linley

ML-Based Coverage Refinement. Innovation in Verification

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3D IC Update from User2User

3D IC Update from User2User
by Daniel Payne on 05-24-2022 at 10:00 am
Categories: EDA, Siemens EDA
1 Comment

FO WLP min

Our smart phones, tablets, laptops and desktops are the most common consumer products with advanced 2.5D and 3D IC packaging techniques. I love seeing the product tear down articles to learn how advanced packaging techniques are being used, so at the User2User conference in Santa Clara I attended a presentation from Tarek Ramadan, 3D IC AE at Siemens EDA.

Tarek Ramadan, 3D IC AE, Siemens EDA

2.5D IC packaging has been accomplished through the use of interposers with silicon or organic substrates, and FO-WLP (Fan-out, Wafer Level Package) is a popular technique. The promise of using chiplets to mix and match IP blocks as dies is another growing trend.

2.5D Packaging
FO-WLP

From the design side of things, an engineer wants to know how the connectivity is defined in these packages, plus how to perform a full assembly physical verification to ensure reliability and high yields. A system-level netlist is the goal, and for packaging that uses a silicon interposer it is Verilog, while for an organic substrate CSV is the common description. With different netlist formats, and even different engineering teams, this creates a communication challenge.

Siemens has created something to help these teams work together on packaging, and they call the product Xpedition Substrate Integrator (xSI) which is a tool used for connectivity planning, optimization and management. Engineers can import and export connectivity in lots of formats (Verilog, CSV, ODB++, LEF/DEF, GDS), and also make interactive and manual assignments. The system netlist output can then be used for LVS (Layout Versus Schematic) and STA (Static Timing Analysis) tools.

Xpediiton Substrate Integrator

You can even perform device transformations or scaling, and xSI has the capacity to handle millions of pins. There are four steps in the xSI flow:

  1. Create a design/floorplan
  2. Create the different parts
  3. Align the 3D-IC system
  4. Apply connectivity to the xSI database

Tarek showed how how parts were created by importing a CSV file, and the example used an interposer with 4 dies and C4, while the package was a BGA and interface C4. The interposer connectivity was defined by Verilog, and then displayed in the Siemens Visualizer Debug Environment.

Interposer connectivity

Physical verification DRC and LVS for individual dies and the silicon interposer are performed using the standard PDK supplied from the foundry. An assembly description is really needed for the positioning of each die on the interposer. The Siemens approach is to use both Xpedition Substrate Integrator and Calibre 3DSTACK tools together for assembly level verification.

Assembly Level Verification Workflow

Q&A

Q: How popular are these tools from Siemens?

A: Since 2017, about 25 customers are using the flow so far. This is really a back-end independent approach. Using both tools in tandem is essential for 3D IC packaging.

Q: Why use an assembly description?

A: It’s the only method to answer the question of where everything is being placed. The assembly can also be checked for consistency. 

Q: What about the chiplet association, UCIe?

A: No EDA company was announced at the formation of UCIe, but stay tuned to see EDA companies joining soon. There’s also the Open Compute Platform – CDX chiplet design exchange kit. The UCIe is trying to standardize how chiplets are assembled together.

Summary

Our semiconductor industry has grown the trend of 2.5D and 3D IC by using advanced packaging approaches, and it’s an engineering challenge to properly capture the system-level connectivity. Package engineers and IC engineers use different tools and file formats, so having a tool flow that knows how to combine information from each discipline makes the task of design and verification tenable.

The Siemens tool Xpedition Substrate Integrator has met the needs of 3D IC design challenges, and supporting Verilog for interconnect makes the flow easier to use. On the physical verification side, a 3D IC assembly description is required, and using the combination of xSI and Calibre 3DSTACK ensures that verification is complete.

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Sensing – Who needs it?

Sensing – Who needs it?
by Dave Bursky on 05-24-2022 at 6:00 am
Categories: Analog Bits, Events, IP

Analog Bits Sensing SemiWiki

In a simple answer – everyone.  A keynote presentation “Sensing the Unknowns and Managing Power” by Mahesh Tirupattur, the Executive Vice President at Analog Bits at the recent Siemens User2User conference, discussed the need and application of sensors in computing and power applications. Why sense? As Mahesh explains, sensing provides the middle ground between the pure analog functions and the digital systems. The need for sensing is everywhere, and in today’s latest system-on-chip designs the challenges start with the doubling of performance while halving the power consumption. With that comes the integration of billions of transistors and if any one component fails, the entire SOC could fail. Those challenges escalate with the use of FINFET transistors due to their exacting manufacturing requirements.

Challenges with such a design include the difficulties of exhaustively verifying the design before tape-out as well dealing with an almost infinite range of manufacturing variations. Additional issues include dealing with dynamic power spikes superimposed on PVT variations in mission mode. Large die sizes with multiple cores can also cause significant local temperature variations of 10 to 15 degrees across the die, and sensing can quickly detect and take corrective actions, such as software load balancing. Process variations can also be detected through the use of multiple Vt devices. Power distribution and power-supply integrity are also challenges for large chips and sensing can monitor and take instantaneous corrective actions at high processing speeds. With large numbers of processing cores on a chip, dynamic current surges can cause internal voltages to exceed functional limits.

As an example, Mahesh examines the design of the world’s largest AI chip, the Cerebras WSE-2. This wafer-sized “chip” has an area of 46,225 mm2 and contains 2.6 trillion transistors, trillions of wires, and 850,000 AI optimized compute cores (see the photo). Fabricated using TSMC’s 7 nm process technology, the device also contains 40 Gbytes of on-chip memory and delivers a 220 Petabit/s fabric bandwidth. Multiple sensors are embedded on the wafer – 840 glitch detectors and PVT sensors designed by Analog Bits provide real-time coverage of supply health, monitoring functional voltage and temperature limits.

The sensors can detect anomalies with significantly higher bandwidth than other solutions that miss short-duration events. Able to provide high-precision real-time power-supply monitoring exceeding 5 pVs sensitivity, the sensor intellectual property (IP) blocks are highly user programmable for trigger voltages/temperature, depth of glitch and time-span of the glitches. The ability to monitor multiple thresholds simultaneously provides designers and system monitors with a wealth of data to optimize the instantaneous current spikes suppression and overall effectiveness. Additionally, the fully-integrated analog macro can directly interface to the digital environment, can be abutted for multiple value monitoring and packs an integrated voltage reference.

Mahesh also sees the need for other power related sensors – on-die PVT sensors with accuracies trimmable to within +/-1C, integrated power-on-reset sensors that detect power stability in both core circuits and I/O circuits, and also offer brown-out detection. These sensors are just one piece of the puzzle that IP designers are facing. We have to design a test chip in a brand new process—it takes us several months to do the design and about nine months to get the test chip back from the fab. Then it may take a year or more for the customer to incorporate the IP in their design. As an IP company our challenges are even greater—customers are not just designing a chip, but designing a system, and that means that they have to co-optimize everything together. Thus, monitoring power is not just the power as a single chip, but power as an entire system and there comes the challenges of voltage spikes and power integrity and those issues, if not sensed and dealt with, can basically kill the whole system. Thus monitoring the thresholds and spikes, and quickly responding to the issues can result in more reliable systems.

In addition to power-related IP blocks, Analog Bits also developed a “pinless” phase-locked loop (PLL) that solves some of the on-chip clocking issues.  The PLL can be powered by the SOC’s core voltage rather than requiring a separate supply pin. That reduces system bill of materials costs by eliminating filters and pins, and the IP can be placed anywhere without and power pad bump restrictions. Last but not least, Analog Bits also has family of SERDES IP blocks that are optimized for high-performance, low-power SOC applications. The IP blocks are available in over 200 different process nodes, including 5 nm (silicon proven), 4 nm, and 3 nm (both in tape out), as well as older nodes, from all major foundries.

Also read:

Analog Bits and SEMIFIVE is a Really Big Deal

Low Power High Performance PCIe SerDes IP for Samsung Silicon

On-Chip Sensors Discussed at TSMC OIP

 

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Unlocking PA design with predictive DPD

Unlocking PA design with predictive DPD
by Don Dingee on 05-23-2022 at 10:00 am
Categories: EDA, Keysight EDA

Predictive DPD virtual test bench

Next up in this series on modulated signals is an example of multi-dimensional EM design challenges: RF power amplifiers (PAs). Digital pre-distortion (DPD) is a favorite technique for linearizing PA performance. Static effects are easy to model and correct, but PAs are notorious for interrelated dynamic effects spoiling EVM and other key metrics. In a shift left, unlocking PA design with predictive DPD transforms how PA manufacturers design for applications. When designers know what to expect, PA manufacturers win more RF system designs faster.

Basics of DPD applied to PAs

Complex waveforms spanning wide bandwidths stress PA designs. Communications “rogue waves” show up with sudden high-power peaks. Under extreme peak-to-average power ratio (PAPR) conditions, balancing requirements for PA energy efficiency, signal quality, and output power level becomes difficult. Performance degrades, PA instability can develop, and sharp signal peaks can create interference affecting more users.

Critical performance metrics like in-band EVM (error vector magnitude) and out-of-band ACLR (adjacent-channel leakage ratio) are first to suffer these signal peaks. EVM reflects how well transmitted symbols match their intended spot in a QAM constellation – see the example for 16-QAM below. If points are closer together than they should be, accurate discrimination between adjacent points gets tougher. For example, 5G EVM specs allow no more than 3.5% total error for 256-QAM modulation in sub-6 GHz systems.

Designers have two fundamental choices. One is backing off to a lower output power, which eases non-linearity. The other is running at higher power levels but compensating for PA non-linearity. DPD is a preferred compensation technique because of its digital flexibility, often included within baseband ASICs or FPGA co-processors. From non-linearity measurements an inverse response is created, linearizing the PA output when the pre-distorter is cascaded in front of it. The magic of DPD is fitting a precise curve. With higher order polynomial representations and more weighting coefficients, the response can be tuned.

 

Dynamic effects weigh in on applications

Assuming one has good non-linearity measurements and a grip on linear algebra, amplifier linearization has mostly been a solvable problem. Historically, PAs were designed, built, then characterized in a lab with pure sine waves. An RF system designer picked up the PA manufacturer’s datasheet, which probably included a PA frequency response curve, then determined how to best fit it in their application.

That was before wideband complex modulated signals became common in RF systems. Hitting difficult specs like EVM suggests designing a DPD-PA combination tuned for a specific waveform. But wireless systems have different complex waveforms. A DPD-PA combo that performs well in one wireless application may hurt EVM performance in others.

Worse still, one DPD-PA implementation may not even hold up in the same application under different conditions. Dynamic interactions between waveform-related effects and operating point-related effects take hold, changing PA performance. Troublesome factors like charge trapping and self-heating, hard to reproduce in physical test setups, create “memory” effects.

Authentic waveforms change the PA design workflow

If we know a PA is going into a 5G, Wi-Fi 7, or similar design with complex modulated signals, and we know non-linearity shows up at high PAPR and crushes EVM, why is it left to RF system integrators to solve, after the fact? Today, we have authentic signals – often from the system specification. We can measure PA non-linearity and derive DPD. In fact, we can explore PA performance for an intended application in virtual space applying predictive DPD as a design tool, then characterize designs in context before shipping them. The physical measurement science looks like this:

A vector signal generator (VSG) fires up an ideal waveform to start. A vector signal analyzer (VSA) measures EVM and other system performance metrics, and iterates the DPD response automatically, adjusting the authentic waveform stimulus. This completely isolates a PA device under test – effects from fixturing and instrumentation are nulled out, leaving the exact PA response in results.

Now bring this concept to virtual space. In Keysight PathWave System Design or PathWave ADS, behavioral models account for detailed real-world effects – non-linearity, memory, bandwidth variations, harmonics, thermal, and more. Every variable can be swept, making hard-to-reproduce effects easier to see in virtual space. Authentic waveforms come from Keysight libraries for 5G, Bluetooth, Wi-Fi, GNSS/GPS, and other systems. With the PA design virtually modeled, the PathWave VTB Engine handles the virtual predictive DPD block.

Steps like compact test signals and fast envelope simulation provide control speed and detail. Instead of a big-bang simulation at the end as a verification step, simulating EVM contours against a parametric scan provides rapid results. Incremental PA design changes address those difficult optimizations for efficiency, signal quality, and output power – in virtual space, before committing to PA hardware.

See what a PA customer sees before they see it

With authentic waveforms and measurements factored into virtual models and simulations, PA manufacturers can evaluate their designs under their customer’s conditions. RF system designers know exactly what they can expect from a PA in their application. Plus, they might be able to borrow the transportable model for their RF system modeling and simulation. This doesn’t mean there must be PAs optimized for each waveform, or that DPD isn’t required to fine-tune a physical RF system design. What it does mean is RF system designers have higher confidence when they select a PA for their application that it will deliver system-level results for them – and that translates to more design wins for the PA manufacturer.

Shifting from thinking of DPD as an after-market product to unlocking PA design with predictive DPD is a straightforward workflow change with a big payoff. Teams don’t need to be experts in DPD theory or implementation to leverage Keysight tools for better results. For more on DPD as a design tool for PAs, see this Keysight video on Practical Power Amplifier Design.

Also read:

Shift left gets a modulated signal makeover

WEBINARS: Board-Level EM Simulation Reduces Late Respin Drama

 

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Protecting High-Speed Interfaces in Data Centers with Security IP

Protecting High-Speed Interfaces in Data Centers with Security IP
by Kalar Rajendiran on 05-23-2022 at 6:00 am
Categories: Events, IP, Synopsys

SoCs Have Many Interfaces That Require Security

The never ending appetite for higher bandwidths, faster data interfaces and lower latencies are bringing about changes in how data is processed at data centers. The expansion of cloud to the network edge has introduced broad use of artificial intelligence (AI) techniques for extracting meaning from data. Cloud supercomputing has resulted in innovative data accelerators and compute architectures within data centers. At the same time, threats are coming from many directions and in many forms. The threat entry could be in the internet communications infrastructure in the form of DoS, BotNet, Ransomware, Spyware, etc. Or it could be via cloud API vulnerabilities and account hijacking. All these threats could be broadly classified into communications attacks, software attacks, invasive hardware attacks and non-invasive hardware attacks.

The combination of the above two trends has increased the need for enhanced data security and data privacy within data centers. The challenge data centers face is how to maintain data security without compromising on throughput and latencies. At the end of the day, it all comes down to enabling security at the chip/SoC level.

Dana Neustadter, Sr. Manager, Product Marketing for Security IP at Synopsys was responsible for presenting at IP-SoC Silicon Valley 2022 last month. Her presentation focused on challenges and ways of protecting data in motion and at rest at data centers. She discusses the trends that are driving heightened requirements and presents SoC solutions for ensuring security of various high-speed interfaces. This post is a synthesis of her presentation. You can download her presentation slides from here.

Requirements for Effective Security Solutions

SoCs incorporate a number of different high-speed interfaces to move data between systems, memories, storage, and peripheral devices. Effective security mechanisms need to protect both data-in-motion as well as data-at-rest. This involves

  • Authentication and Key Management for implementing

– Identification & Authentication

– Key generation

– Key distribution

– Control

  • Integrity and Data Encryption between endpoints for ensuring

– Confidentiality

– Integrity

There are of course challenges when it comes to the implementation of these security mechanisms. How to add security on the data path while maintaining high throughput at low latencies? How to securely identify the data path endpoints without adding a large processing overhead? How to establish a trusted zone for managing and handling keys without adding to silicon area?

Key Aspects of Delivering Effective Security Solutions

There are upcoming standards for building trusted virtual machines at the application core/logic level for handling data paths from PCIe and CXL interfaces. These standards are being driven respectively by PCI-SIG and CXL Consortiums.

Meanwhile the areas of authentication and key management and integrity and data encryption are well defined and driven by existing standards.

  • Authentication, attestation, measurement, and key exchange are implemented by the following standards.

-DMTF: Security protocol and Data Module (SPDM), Management Component Transport Protocol (MCTP)

-PCI-SIG: Component Measurement and Authentication (CMA), Data Object Exchange (DOE), Trusted Execution Environment I/O (TEE-I/O)

  • The integrity and data encryption (IDE) component that addresses the confidentiality, integrity and replay protection is based on the AES-GCM crypto algorithm and is defined by PCIe 5.0/6.0 and CXL 2.0/3.0 standards.

Synopsys’ Security IP Offerings

Synopsys offers a comprehensive set of IP offerings to enable security against data tampering and physical attacks. The following chart shows an example data center networking SoC showing various Synopsys Security IP to secure the data.

PCIe 5.0/ PCIe 6.0 IDE Security Modules

Integrity and Data Encryption (IDE) for PCIe is offered through a PCIe IDE Security Modules. There is a version available for PCIe 5.0 that supports all down speeds. And a separate version supporting the latest generation PCIe 6.0 and all down speeds. These modules work as plug-and-play with Synopsys PCIe controllers to match clock configurations, data bus widths, and lane configurations. The packet encryption, decryption and authentication are based on highly efficient AES-GCM crypto with very low latency. The modules are FIPS 140-3 certification ready.

CXL 2.0 IDE Security Module

As with the PCIe IDE security modules, the CXL security module  is standards compliant and seamlessly integrates with Synopsys CXL controllers. All three protocols, CXL.io, CXL.cache, CXL.mem are supported, with latency as low as 0 cycles for  .cache/.mem protocols in skid mode. This IP is also ready for FIPS 140-3 certification.

Inline Memory Encryption (IME) Security Module

This security module uses the AES-XTS algorithm with two sets of 128-bit or 256-bit keys, one for data encryption/decryption and another for tweak value calculation and is FIPS 140-3 certification ready. The memory encryption subsystem handles encryption, decryption, and management of tweaks and keys with very low latency. Other key features include full duplex support for read/write channels, efficient and protected key control and refresh, and a bypass mode.

Hardware Secure Module with Root of Trust

This security module provides a Trusted Execution Environment (TEE) to manage sensitive data and operations. It is the foundation for secure remote lifecycle management and service deployment. Key security features include a secure boot, secure authentication/debug and key management. Secure instruction and data controllers are included to provide external memory access protection and runtime tamper detection. Scalable cryptography options are available to accelerate encryption, authentication and public key operations.

Summary

Secure infrastructure is key to protecting data. Authentication and key management in the control plane and integrity and data encryption in the data plane are essential components of a complete security solution. Securing high-speed interfaces needs to be highly efficient with optimal latency. Synopsys provides complete solutions to secure SoCs, their data, and communications.

For more information, visit Synopsys Security Modules for Standard Interfaces

Also Read:

Bigger, Faster and Better AI: Synopsys NPUs

The Path Towards Automation of Analog Design

Design to Layout Collaboration Mixed Signal

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Double Diffraction in EUV Masks: Seeing Through The Illusion of Symmetry

Double Diffraction in EUV Masks: Seeing Through The Illusion of Symmetry
by Fred Chen on 05-22-2022 at 7:00 am
Categories: Events, Lithography

Double Diffraction in EUV Masks

At this year’s SPIE Advanced Lithography conference, changes to EUV masks were particularly highlighted, as a better understanding of their behavior is becoming clear. It’s now confirmed that a seemingly symmetric EUV mask absorber pattern does not produce a symmetric image at the wafer, as a conventional DUV mask would [1, 2]. The underlying reason for this is the mask is illuminated by a spread of angles skewed to one side of the vertical axis. Each angle has a different reflection from the multilayer of the EUV mask. Moreover, the EUV light is diffracted twice, one time before entering the multilayer, and a second time after exiting the multilayer (Figure 1).

Figure 1. Double diffraction in an EUV mask. Each color represents a particular family of diffraction orders originating from one reflected diffraction order from the first diffraction of light entering the multilayer.

The first diffraction from an array of lines on the EUV mask with pitch p produces a Fourier series of the form

… + A_1 exp[-i 2pi x/p] + A0 + A1 exp[i 2pi x/p] +…

Each series term An exp [i 2pi n x/p] represents a diffraction order propagating in a given direction. Each propagating direction leads to a different multilayer reflectance Rn for that order.

… + A_1 R_1 exp[-i 2pi x/p] + A0 R0 + A1 R1 exp[i 2pi x/p] +…

Passing through the array again when exiting the multilayer, each order generates a second set of diffraction orders, with their amplitudes labeled by B instead of A. The directions of these second sets of diffraction order overlap those of the first. By combining the waves coherently propagating in the same directions, we get:

… + [… + A_1 R_1 B0 + A0 R0 B_1 + A1 R1 B_2 + …] exp[-i 2pi x/p] + [… + A_1 R_1 B1 + A0 R0 B0 + A1 R1 B_1 + …] + [… + A_1 R_1 B2 + A0 R0 B1 + A1 R1 B0 + …] exp[i 2pi x/p] + …

Since the mask structures in the array are symmetric as fabricated, we may approximate A1 = A_1, B1 = B_1. However, R1 does not qual R_1, as they correspond to different angles, and even a seemingly small angular difference can drop the reflectance significance. With this consideration, when we compare the -1st harmonic amplitude [… + A_1 R_1 B0 + A0 R0 B_1 + A1 R1 B_2 + …] with the 1st harmonic amplitude [… + A_1 R_1 B2 + A0 R0 B1 + A1 R1 B0 + …], they are not equal. In a symmetric structure that a rectangular profile is expected to be, these should be equal. However, physically, the structure is not behaving so much as a rectangular wave profile but more like a trapezoidal wave profile, largely due to the shadowing effect from the off-axis incident direction of the light (Figure 2). The effective slope of the sidewall is dependent on the shadowing, and hence, the illumination angle.

Figure 2. (Left) A conventional photomask provides a symmetric absorption profile. (Right) On the other hand, for an EUV mask, the trapezoidal profile is a more accurate depiction of the asymmetry effects from shadowing, even though the EUV mask structures themselves are symmetric as fabricated. The illumination angle(s) will determine the shadowing, and hence, the effective slope angle.

Relying on a trapezoidal absorption profile for the mask is a notable departure from the symmetric rectangular profile that has always been used in conventional DUV photomasks. It causes the numerous anomalies of EUV imaging that have already been published over the many years of EUV development. As EUV lithography especially makes more use of dipole illumination (beams coming from two different angles), the angle asymmetry between +1st and -1st diffraction orders becomes more relevant [3].

References

[1] C. van Lare, F. Timmermans, J. Finders, “Mask-absorber optimization: the next phase,” J. Micro/Nanolith. MEMS MOEMS 19, 024401 (2020).

[2] A. Erdmann, H. Mesilhy, P. Evanschitzky, “Attenuated phase shift masks: a wild card resolution enhancement for extreme ultraviolet lithography?,” J. Micro/Nanolith. MEMS MOEMS 21, 020901 (2022).

[3] https://www.linkedin.com/pulse/pattern-shifts-induced-dipole-illuminated-euv-masks-frederick-chen; https://semiwiki.com/lithography/305907-pattern-shifts-induced-by-dipole-illuminated-euv-masks/

Also Read:

Demonstration of Dose-Driven Photoelectron Spread in EUV Resists

Adding Random Secondary Electron Generation to Photon Shot Noise: Compounding EUV Stochastic Edge Roughness

Intel and the EUV Shortage

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Take a Leap of Certainty at DAC 2022

Take a Leap of Certainty at DAC 2022
by Daniel Nenni on 05-22-2022 at 6:00 am
Categories: Ansys, Inc., EDA, Events

Ansys DAC 2022

The live events I have attended thus far this year have been very good. As much as I liked the virtual events, attending in the comfort of my home or sailboat, it is great to be live and networking inside the semiconductor ecosystem, absolutely.

Ansys has been a great supporter of the Design Automation Conference but this year they are going big. Ansys is also a strong supporter of SemiWiki and a joy to work with.

We have written extensively about 3D-IC, 2.5D/3D packaging, power integrity, and other multiphysics challenges so this will be a great time to sync up on where we are today and what Moore’s Law has in store for us tomorrow. Bespoke Silicon is also a trending topic as the systems companies make their own chips so you don’t want to miss that.

Ansys is also great at customer engagements so stop by their theater to see who is using what tools and why. Here is the Ansys preview, I hope to see you  at DAC 2022!

Request a meeting or demo

WE’RE SHOWING THE LATEST IN DESIGN TECHNOLOGY

The semiconductor and electronics industries collide as 3D-IC technology, enabling companies to design differentiating bespoke silicon. The advent of 3D-IC requires more physics domains in a multiphysics challenge requiring new tools and approaches to building electronic design teams. At DAC 2022, we’ll share the latest technologies for 5nm power integrity signoff, dynamic voltage drop coverage, electrothermal signoff for chips & PCBs, advanced 2.5D/3D packaging, and photonic design.

See the Latest Multiphysics Signoff Technology

Did you know? Ansys delivers the industry’s broadest range of foundry-certified golden signoff tools for semiconductor design, electronic design, and full system design.

Stop by our booth to see the latest advances in Power Integrity, Thermal Analysis, Electromagnetics, and Photonics for semiconductor and board designers. Our technical experts are available to answer your questions. Or you can schedule a meeting in our booth. 

Grab a seat in our booth theater featuring short presentations by our customers, partners, and technologists on a variety of topics at regular intervals during the exhibit hours. While there, you just might pick up a unique NFT.

Learn From the Experts at DAC

We’re participating in the DAC Pavilion Roundtable Discussion on “Bespoke Silicon“ where industry experts look at the technical and business implications of companies increasingly turning to tailored silicon solutions to differentiate their key products.

Listen to Ansys customers present their actual semiconductor projects during DAC’s Engineering Tracks and Poster Sessions, listed below.

WHAT ARE THE BIG OPPORTUNITIES IN THE NEXT RENAISSANCE OF EDA?

Research Panel: Tuesday, July 12th, 3:30pm-5:30pm PDT
Prith Banerjee, CTO, Ansys

NEW DIRECTIONS IN SILICON SOLUTIONS

Engineering Track: Tuesday, July 12th, 3:30pm-5:00pm PDT
Norman Chang, Fellow & Chief Technologist, Ansys

BESPOKE SILICON-TAILOR MADE FOR MAXIMUM PERFORMANCE

DAC Pavilion Panel: Wednesday, July 13th, 2:00pm-2:45pm PDT
John Lee, VP & GM, Electronics & Semiconductors, Ansys

About Ansys

If you’ve ever seen a rocket launch, flown on an airplane, driven a car, used a computer, touched a mobile device, crossed a bridge or put on wearable technology, chances are you’ve used a product where Ansys software played a critical role in its creation. Ansys is the global leader in engineering simulation. Through our strategy of Pervasive Engineering Simulation, we help the world’s most innovative companies deliver radically better products to their customers. By offering the best and broadest portfolio of engineering simulation software, we help them solve the most complex design challenges and create products limited only by imagination. Founded in 1970, Ansys is headquartered south of Pittsburgh, Pennsylvania, U.S.A. Visit www.ansys.com for more information.

Ansys and any and all ANSYS, Inc. brand, product, service and feature names, logos and slogans are registered trademarks or trademarks of ANSYS, Inc. or its subsidiaries in the United States or other countries. All other brand, product, service and feature names or trademarks are the property of their respective owners.

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Bespoke Silicon is Coming, Absolutely!

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