SemiWiki – Page 182 – The Open Forum for Semiconductor Professionals

Podcast EP176: Implementing End-to-End Security with Axiado’s New Breed of Security Processor

Podcast EP176: Implementing End-to-End Security with Axiado’s New Breed of Security Processor
by Daniel Nenni on 08-11-2023 at 10:00 am

Dan is joined by Tareq Bustami, senior vice president of marketing & sales, Axiado. Tareq has more than 20 years of experience in the semiconductor and networking industries. Before joining Axiado, he led NXP’s embedded processors for the wired and wireless markets, and was in charge of growing multi-core processor solutions for enterprise, data center infrastructure and general embedded and industrial markets.

Tareq describes Axiao’s unique and comprehensive approach to security. He provides details about its trusted control/compute unit (TCU) AI-driven hardware security platform. A broad look at the challenges of implementing end-to-end security is presented along with a discussion of how Axiado’s technology addresses these challenges.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

August 11, 2023August 9, 2023

The Recovery has Started and it’s off to a Great Start!

The Recovery has Started and it’s off to a Great Start!
by Malcolm Penn on 08-11-2023 at 6:00 am
Categories: Events, Future Horizons, Semiconductor Services

August’s WSTS Blue Book showed Q2-2023 sales rebounding strongly, up 4.2 percent vs. Q1, heralding the end of the downturn and welcome news for the beleaguered chip industry.

The really good news, however, was that the downturn bottomed one quarter earlier than previously anticipated. This pull-forward only added a modest US$11 billion to Q2’s US$ 244 billion sales but this was enough to swing Q2’s growth from minus 5.0 percent to plus 4.2 percent.

A small change in the numbers at the start of the year makes a huge difference to the quarterly growth rates and hence the final year-on-year number.

Market Detail

The market turnaround was driven by a dramatic change in the Asia/Pac region, with 5.4 percent month-on-month growth, followed by the US (plus 3.5 percent), Japan (plus 2.1 percent) and Europe (plus 1.8 percent).

On an annualised basis, Q2-2023 was down 17.3 percent vs. Q2-2023, with Asia/Pac down 22.6 percent, the US down 17.9 percent, Japan down 3.5 percent with Europe, the only region showing year-on-year growth, at plus 7.6 percent.

The near-term market outlook is starting to look a lot stronger, driven by the positive impact of the inventory burn, stronger than expected resilience in the global economy, especially in the USA, and a seemingly robust demand boost from the emerging AI market.

Forecast Summary

Looking ahead to the second half of the year, the overall industry consensus has now (mostly) acknowledged a likely double-digit decline for 2023 vs. the ‘positive growth’ positions predicted this time last Year.

Source: SEMI/Future Horizons

Future Horizons stood alone in the crowd when we first published our 2023 double-digit decline forecast 15 months ago in May 2022, likewise too when we stood by that number at our January 2023 Industry Update Webinar when all others, bar one, were predicted a very mild downturn followed by a sharp V-shaped rebound in 2024.

The stronger than expected second-quarter results will now push our 2023 forecast beyond the bull end of our January 2023 forecast scenario, but our longer-term concerns, re the still ongoing uncertain economic outlook and the excess CapEx spending, show no signs yet of abatement.

Over-capacity is the industry’s number one enemy, depressing ASPs and condemning the industry to low dollar value growth. An economic slowdown will nip any recovery in the bud.

Market Outlook

With two of the four industry fundamentals, unit sales and ASPs, now slowly but surely rebalancing, the havoc and inevitable consequences of the preceding supply-side shortage-induced market boom are now starting to recede. The stage is now set for a return to industry growth, but from a much-reduced base.

The size and shape of the recovery will depend on the potentially derailing impact of capacity (over-investment) and demand (the economy), the former of which is not looking healthy, and the latter still steeped in mixed signals and uncertainty.

That said, 2023 will undoubtedly transpire to have been a line in the sand; and 2024 will equally clearly be better. The recovery has got off to a great start, but its pace and form have yet to be determined.

We will be covering all this, together with an update to our outlook for 2023-24, at our forthcoming Industry Update Webinar on Tuesday 12 September at 3pm UK BST (GMT+1). Register now at:

https://us02web.zoom.us/webinar/register/7416911384194/WN_akISM9QxS8uNZS_oihzqFQ

Also Read:

The Billion Dollar Question – Single or Double Digit Semiconductor Decline

The Semiconductor Market Downturn Has Started

Semiconductor Crash Update

August 10, 2023August 10, 2023

Japan’s Foundry Morgana Part II

Japan’s Foundry Morgana Part II
by Karl Breidenbach on 08-10-2023 at 10:00 am
Categories: Foundries
2 Comments

Japan’s Foundry Morgana: A Journey from Mirage to Reality?Three years ago, I wrote an article about Japan’s semiconductor industry under the title “Japan’s Foundry Morgana.” Back in September 2020, I analyzed the decline of Japan’s once world-leading semiconductor sector and the ambitious plans for inviting TSMC to build an advanced process fab. Who could have imagined that by 2023, fueled by the experiences from the semiconductor crisis, the plans to revive the Japanese foundry footprint would have advanced at such quick pace and determination. It’s worth looking again at what happened so far and if Japan could be a blue print for other regions on the quest to semiconductor supply resilience.

A Look Back: The State of the Japanese Semiconductor Industry

In the late 1980s, Japan emerged as a global leader in semiconductors, holding strong alongside the US. Home to over 30 large-scale industry players like Renesas, Hitachi, Denso, Fujitsu, and Mitsubishi Electronics, Japan boasted a robust semiconductor ecosystem. By 1990 Japanese IDM’s NEC, Toshiba and Hitachi had taken the top three positions in the world-wide semiconductor sales ranking, just ahead of Intel and Motorola.

Top 10 Worldwide Semiconductor Sales Leaders from 1985 to 2021, Source: IC Insights

However, since the year 2000, Japan’s share of international IC exports declined sharply, dropping from 14% to less than 5% by 2020. Despite losing ground, some Japanese IDMs continued to excel in specialized segments like power electronics and optical CMOS sensors.

Japanese silicon foundries primarily arose as carve-outs from leading IDMs, but they struggled to keep up with rivals in Taiwan, China, and the US. Japan held only 2% of global foundry capacity as of 2020. Factors such as late market entry into the foundry business, a lack of cost-containment strategies, and a narrow market segment focus led to the decline of Japan’s foundry ecosystem.

The completion of Nuvoton’s acquisition of Panasonic’s semiconductor unit in September 2020 marked a symbolic end to the Japan-owned foundry landscape, leaving a limited number of small-scale foundries.

The New Landscape: Attracting TSMC and Rebuilding the Foundry Sector

Fast forward to today, and Japan’s semiconductor industry is writing a new chapter. The once ambitious plan to invite TSMC has materialized, resulting in TSMC’s agreement to build two fabs in Japan. Backed by extensive government funding, these fabs symbolize a fresh start and an alignment with the global semiconductor landscape.

Japan’s foundry landscape as of 2023, Source: Own research

The Japanese government’s engagement in this venture is unprecedented, pledging to shoulder a significant portion of the construction costs. Leaders of the ruling party’s lawmaker coalition on chips recognize this as a national strategy, part of Japan’s efforts to revive its domestic chipmaking industry, a sector that is viewed as crucial for growth and economic security.

The joint effort between Hitachi, Renesas, Toshiba, and the Japanese Ministry of Economy signifies a strategic shift. It’s not just about reviving the Japanese-owned foundry sector; it’s about embracing international collaboration, recognizing the importance of supply security, and focusing on processes that align with Japan’s core strengths.

The Rise of Rapidus: A Bold Leap Forward

Alongside the collaboration with TSMC, Japan’s ambitious project Rapidus is a critical piece of the puzzle. Aiming for 2nm production in 2027, Rapidus represents a daring and costly venture. Supported by a consortium that includes IBM and backed by the Japanese government and large conglomerates, Rapidus seeks to reshape Japan’s semiconductor landscape by leapfrogging several generations of nodes.

The endeavor is both extremely challenging and tremendously expensive. Modern fabrication technologies are expensive to develop in general. Rapidus itself projects that it will need approximately $35 billion to initiate pilot 2nm chip production in 2025, and then bring that to high-volume manufacturing in 2027.

Despite the high stakes, the vision is clear and backed by strong commitment. Rapidus aims to serve a limited but significant client base, including tech giants like Apple and Google, focusing on quality and innovation. The focus on limited customers is a strategic move to secure enough demand and revenue to recover massive investment while avoiding emulation of TSMC’s extensive client base.

Rapidus’ success holds much significance for Japan’s advanced semiconductor supply chain, symbolizing more than just a money-making venture but a catalyst for revitalizing the Japanese industry. The Japanese government views it as a critical step towards creating more opportunities for local chip designers, even if immediate success may not be guaranteed.

Conclusion: From Mirage to Reality, A Blueprint for Others?

The reference to “Foundry Morgana” or fata morgana in my initial article resonated with the elusive, almost mythical nature of Japan’s semiconductor revitalization efforts. However, today’s landscape shows a transformation from illusion to reality.

With TSMC’s strategic presence and the pursuit of Rapidus, Japan demonstrates a new level of commitment. It is embracing both its past strength and future potential, rebuilding its foundry landscape with international collaboration, and aligning with global advancements.

Japan’s Foundry Morgana is no longer just a distant reflection. It’s a (potential) reality ;-), emerging on the horizon as a renewal of semiconductors Made in Japan.

The dynamics between Rapidus and TSMC and the larger global context add more intrigue to Japan’s semiconductor industry’s resurrection. The potential impact of geopolitics, market cap, governmental subsidization, and known knowns regarding yields and timetables further adds to the complexity of this journey.

Furthermore, Japan’s approach to revitalizing its semiconductor industry may serve as a blueprint for other regions seeking to enhance their own technological prowess. Europe, for example, with its ambitions to grow its semiconductor manufacturing and reduce dependence, could look to Japan’s strategy for inspiration.

The Synopsys VC Formal group have a real talent for finding industry speakers to talk on illuminating outside-the-box-topics in formal verification. Not too long ago I covered an Intel talk of this kind. A recent webinar highlighted use of formal methods used together with a cool technique I have covered elsewhere called Quick Error Detection (QED). This for me is a good example of what really makes formal so fascinating – not so much the engines behind the scenes as the intellectual freedom they enable in solving a problem. Frederik Möllerström Lauridsen, a verification engineer at SyoSil, shared his experience using this method for Synopsys VC Formal for proofs on a RISC-V core.

VC Formal Enabled QED Proofs

The verification objective

Considering only the base ISA plus possible custom extensions, Frederick wanted a generic setup for RISC-V cores, in part through how they define their SVA assertions. He doesn’t go into detail in his talk, but I believe this means assertions which reference only the start and end of the pipeline, not the internals or the number of cycles required to complete. His goal is to detect both single instruction bugs and multi-instruction bugs. Single instruction bugs are relatively easy to find, but multi-instruction bugs are harder to uncover thanks to context dependent stalls without which for example register read/write conflicts might occur.

Single-instruction bugs (eg does an ADD really add) are not context dependent so can be checked by running the instruction through an otherwise empty pipeline. But multi-instruction bugs are context specific. How can you verify against all legal contexts? To see how, first you need to understand a little about QED.

QED

Quick Error Detection (QED) is a method first invented for post-silicon validation. There you start with machine-level code and regularly duplicate instructions reading and writing through a parallel set of registers / memory locations. You then compare original values with duplicated values; a difference signals an error. Similar techniques are migrating to pre-silicon verification, for an interesting reason. The intent is to regularly compare consistency between parallel implementations, with the promise that root cause errors may be caught long before being flagged by some more functionally meaningful assertion we might think to write. (Incidentally, this technique is not limited to formal verification. It is just as valuable in dynamic verification.)

Combining formal methods and QED

To apply QED you need a reference design and a design under test (DUT). Here the reference design is a single-instruction pipeline test, eg pushing an ADD instruction through an otherwise empty pipeline. In parallel the DUT will push though the same instruction, but how do you define context as an arbitrary selection of possible surrounding instructions? For this Frederick used a variant on QED called C-S²QED.

Without dropping too much into the technical weeds, S² means “symbolic state”, which allows for arbitrary instructions going through the pipeline, constrained so that the first instruction entering the pipeline is the same as the instruction entering the reference pipeline. The “symbolic” part of this is key. It is not necessary to define what other instructions are going through. These are only constrained to be legal instructions. Since we are applying formal methods, all possibilities will be considered together in proofs. The other neat trick that Frederick applied was first to demonstrate that all instructions would pass through the pipeline within at most a fixed number of cycles, providing a limit for bounded proofs.

Now using the QED methodology, comparing the reference design and DUT through formal methods provides proof that there are no multi-instruction bugs in the pipeline implementation, or it provides a counterexample. Pretty cool! Frederick did acknowledge that they had not extended their method to any of the standard RISC-V ISA extensions (M, A, F, etc) though you could use VC Formal DPV for the M extension and no doubt clever folks can come up with creative possibilities for other extensions.

Very cool stuff. You can register to watch the webinar HERE.

For enthusiasts of this line of thinking check out a blog I wrote back in 2018, on the Wolper method to verify the correctness of data transport logic in network switches or on-chip interconnects or memory subsystems. I love the way formal has been applied so creatively in QED and in Wolper. There must be more opportunities like this 😊

August 9, 2023August 9, 2023

Elon Musk is Self-Aware

Elon Musk is Self-Aware
by Roger C. Lanctot on 08-09-2023 at 10:00 am
Categories: Automotive

“I think we’ll be better than human by the end of the year.” – Elon Musk, CEO, Tesla

Parsing the impact of the latest Tesla earnings call featuring CEO Elon Musk has become an eerie out-of-body experience. The comments of the CEO are simultaneously assessed in real time and in retrospect as they are being spoken. It is automotive history in the making – a latter day Henry Ford undoing much of what that scion created. Think: re-vision (not division) of labor.

There is, of course, the prosaic assessment of projected earnings hits or misses – and the “markets” chose a negative response to Musk’s otherwise euphoric take on the company’s prospects. What was hard to ignore was the company’s ongoing success in the face of multiple macroeconomic obstacles and Musk’s own musings on his own path.

At one point he described himself as “the boy who cried FSD” – referring to the controversial full-self-driving capability available to new Tesla buyers for $15,000. This is the same FSD that is still not quite living up to its name.

Musk’s level of self-awareness is hard to ignore or avoid. One can only imagine what it’s like to read about yourself on a daily, hourly basis. In real-time Musk must come to grips with who he is, who he thinks he is, and who everyone else thinks he is or what they think of him.

Maintaining one’s grip on reality in these circumstances is itself no small feat. For Musk it is made even more complex by the fact that there is the Tesla Musk, the SpaceX Musk, the Twitter Musk, the x.AI Musk etc. etc. Everyone has their own Musk.

The Tesla Musk is probably the most interesting and palatable. But the Tesla Musk is not without his skeptics and critics taking into account unfulfilled full-self-driving forecasts, ongoing investigations of fatal crashes, and price cut and vehicle delivery flip-flops.

The most disturbing aspect of the latest Tesla earnings call with Musk is his comprehensive grasp of the technical issues (software, AI, battery tech) facing his company and the industry and his willingness to discuss those challenges and the company’s plans to overcome them. Perhaps even more important is Musk’s discussion of how the company has already overcome them.

Musk wastes no time getting to two of what may be the biggest questions facing the automotive industry:

How to enhance cars in such a way to improve safety and reduce highway fatalities.
How to hire and retain talent to work on cars.

Musk says nothing of “vision zero” platitudes and plans. After all, talking about vision zero, these days, is like talking about climate change. We feeble little humans have set off global climate shifts that will require decades if not centuries to reverse. In the same way, a million human beings are dying annually on a global scale on roadways – a reality that will be equally difficult to correct.

As the pied piper of electric vehicles, Musk is taking on both these global challenges at once – and can already point to some success.

For Musk the answer lies in a unified theory of “autonomy.” It will take mountains of data to improve and achieve full-self-driving, which will require a limitless supply of processing power (much of it from Nvidia), to achieve the objective of superhuman driving capability – a 10x-100x improvement on human driving – which still won’t get “us” to zero fatalities.

Just as Musk acknowledged, on the earnings call, the expanding adoption of Tesla’s fast charging connector and network technology by car makers such as General Motors and Ford Motor Company, he hinted at the prospect of the first car maker licensee of Tesla FSD technology. No names yet.

No other car company is even close to the required level of data collection and processing that Musk has already put in place and is expanding daily. In the context of achieving this ultimate goal of safe self-driving, the $15,000 price tag for FSD will seem trivial, he says, but even so a subscription-based alternative could be made available.

In a world where we have routinely been “sold” by “legacy” auto makers on the wonders and attractions and liberation of human driving, Musk has made machine-assisted driving aspirational. It is for this and other reasons that analysts and shareholders hang on his every word.

Notably, Tesla is fundamentally rewiring the consumer mindset regarding cars and driving in such a way that it is now short-circuiting the value of mass market automobile advertising. Increasingly, television, radio, or Internet advertising targeted at traditional internal combustion vehicle value propositions is missing its mark. Tesla does little advertising of its own.

I may only be speaking for myself, but as an EV owner my experience of TV advertising for ICE vehicles has been permanently altered. These ads are only interesting to me, now, as historical artifacts.

As for hiring and retaining the personnel necessary to achieve Musk’s dreams and Tesla’s objectives, Musk talks about interviewing and recruiting candidates who essentially don’t want to work for Tesla. By expanding his endeavors with SpaceX and, most recently, x.AI Musk has been able to hire and retain top performers whose contributions to other efforts convey a collateral benefit to Tesla.

Musk is following in the footsteps of auto industry founders who also diverted the efforts of their engineers into non-automotive endeavors. Car companies today have strangely lost the luster of past non-automotive forays.

At the very beginning of the earnings call Musk noted record vehicle production (nearing 2M annualized) and revenue ($25B) and talked about anticipating “quasi-infinite” demand for a future dedicated “robotaxi.” If any organization could make robotaxis popular, it would be Tesla.

Musk has thrust Tesla to the forefront of autonomous vehicle and artificial intelligence development. While we worry about the machines becoming self aware, a self aware Elon Musk is oddly reassuring. He knows how he sounds. He knows what we’re thinking – even as he is altering the way we think. Don’t be frightened, but do be aware, like Elon.

Also Read:

Xcelium Safety Certification Rounds Out Cadence Safety Solution

Sondrel Extends ASIC Turnkey Design to Supply Services From Europe to US

Automotive IP Certification

August 9, 2023August 22, 2023

Insights into DevOps Trends in Hardware Design

Insights into DevOps Trends in Hardware Design
by Bernard Murphy on 08-09-2023 at 6:00 am
Categories: EDA, Perforce

Periodically I like to check in on the unsung heroes behind the attention-grabbing world of design. I’m speaking of the people responsible for the development and deployment infrastructure on which we all depend – version control, testing, build, release – collectively known these days as DevOps (development operations). I met with Simon Butler, GM of the Methodics BU at Perforce to get his insights on directions in the industry. Version control proved to be just the tip of what would eventually become DevOps. I was interested to know how much the larger methodology has penetrated the design infrastructure (hardware and software) world.

Software and DevOps

DevOps grew up around the software development world, where it is evolving much faster than in hardware development. Early in-house Makefile scripts and open-source version control (RCS, SCCS) quickly progressed into more structured approaches, built around better open-source options combined with commercial tools. As big systems based on a mix of in-house and open/commercial development grew and schedules shrank, methods like CI/CD (continuous integration / continuous deployment) and agile became more common, spawning tools like Jenkins. Cloud-based CI/CD added further wrinkles with containers, Kubernetes and microservices. How far we have come from the early days of ad-hoc software development.

Why add all this complexity? Because it is scalable, far more so than the original way we developed software. Scalable to bigger and richer services, to larger and more distributed development teams, to simplified support and maintenance across a wide range of platforms. It is also more adaptable to emerging technologies such as machine learning, since the infrastructure for such technologies is packaged, managed, and maintained through transparent cloud/on-prem services.

What about hardware design?

Hardware design and design service teams have been slower to fully embrace DevOps, in some cases because not all capabilities for software make sense for hardware, in other cases because hardware teams are frankly more conservative, preferring to maintain and extend their own solutions rather than switch to external options. Still, cracks are starting to appear in that cautious approach.

Version control is one such area. Git and Subversion are well established freeware options but have scaling problems for large designs across geographically distributed development, verification, and implementation organizations. Addressing this challenge is where commercial platforms like Perforce Helix Core can differentiate.

In more extensive DevOps practices, some design teams are experimenting with CI/CD and Agile. During development, a new version of a lower level is committed after passing through quality checks. That triggers workspaces ready to roll with subset regression tests, running the new candidate automatically and all managed by Jenkins.

Product lifecycle management (PLM) has been common in large system development for decades. Cars, SoCs, and large software applications are built around many components, some legacy, some perhaps open source, some commercial. Each evolves through revisions, some of which have known problems discovered in design or in deployment, some are adapted to special needs. Certain components may work well with other components but not with all. PLM can trace such information, providing critical input to system audits/ signoffs.

In managing such functions in DevOps, design teams have two choices – fully develop their own automation or build around widely adopted tools. Some go for in-house for all the usual reasons, though management sentiment is increasingly leaning to proven flows in response to staffing limitations, risks in adding yet more in-house software, and growing demand for documented traceability between requirements, implementation, and testing. While management attitudes are still evolving, Simon believes organizations will inevitably move to proven flows to address these concerns.

Cloud

The state of DevOps adoption in hardware is somewhat intertwined with cloud constraints. For software there are real advantages to being in the cloud since that is often the ultimate deployment platform. The same case can’t be made for hardware. Simon tells me that based on multiple recent customer discussions there is still limited appetite for cloud-based flows, mostly based on cost. He says all agree with the general intent of the idea, but these plans are still largely aspirational.

This is true even for burst models. For hardware design and analytics, input and output data volumes are unavoidably high. Cloud costs for moving and storing such volumes are still challenging, undermining the frictionless path to elastic expansion we had hoped for. Perhaps at some point big AI applications only practical in the cloud (maybe generative methods) may tip the balance. Until then, heavy cloud usage beyond the cloud in-house design groups may struggle to move beyond aspirational.

Interest in unifying hardware and software DevOps

Are there other ways in which software and hardware can unify in DevOps? One trend that excites Simon is customers looking for a unified software and hardware Bill of Materials.

The demand is clear visibility into dependencies between software and hardware, for example does this driver work with this version of the IP? Product teams want to understand re-use dependencies between stack hardware and software components. They need insight into questions which PLM and traceability can answer. In traceability, one objective is to prove linkage between system requirements, implementation, and testing. Another is to trace between component usages and known problems in other designs using the same component. If I find a problem in design I’m working on right now, what other designs, quite possibly already in production, should I worry about? Traceability must cross from software to hardware to be fully useful in such cases.

Interesting discussion and insights into the realities of DevOps in hardware design today. You can learn more about Perforce HERE.

August 8, 2023September 22, 2023

Breakthrough Gains in RTL Productivity and Quality of Results with Cadence Joules RTL Design Studio

Breakthrough Gains in RTL Productivity and Quality of Results with Cadence Joules RTL Design Studio
by Kalar Rajendiran on 08-08-2023 at 10:00 am
Categories: AI, Cadence, EDA

Register Transfer Level (RTL) is a crucial and valuable concept in digital hardware design. Over the years, it has played a fundamental role in enabling design of complex digital chips. By abstracting away implementation details and providing a clear description of digital behavior, RTL has contributed significantly to the advancement and widespread adoption of digital design methodologies. It abstracts away the specific implementation details and technology-dependent aspects, providing a more manageable and technology-agnostic representation of the design. RTL provides a basis for design exploration and optimization. Engineers can modify the RTL code to explore various design alternatives and identify the most efficient solutions.

While the chip design process benefits tremendously from the use of RTL, the designs need to be synthesized and taken through the layout process before the chips can be manufactured. Tools for synthesis and place and route rely on RTL as input to generate the physical layout of the chip. This transition comes with several challenges that designers need to address to ensure a successful and optimal chip implementation. Physical design constraints such as area, power and routability constraints must be satisfied during the layout process while considering the characteristics and limitations of the target process technology and manufacturing process. Power integrity, signal integrity, design for manufacturability (DFM) and many more requirements need to be addressed as well.

As designs grow in complexity, the productivity and turnaround time become significant challenges during the RTL-to-layout transition. The RTL-to-layout transition often involves iterative processes where designers must go back to the RTL level to make modifications and then repeat the layout process. Efficient iteration management is crucial to avoid time-consuming and costly iterations. It is in this context that Cadence’s recent announcement highlighting the delivery of the Joules RTL Design Studio takes significance. It promises to deliver up to 5X faster RTL convergence and up to 25% improved Quality of Results (QoR) when compared with traditional RTL design approaches.

Actionable Intelligence

The driving force behind the Joules RTL Design Studio lies in its ability to provide RTL designers with actionable intelligence and rapid insight into physical effects. This capability enables design teams to address potential issues early in the design process, leading to reduced iterations, thus speeding time to market. Front-end designers can now access digital design analysis and debugging capabilities from a single, unified cockpit, streamlining the design process and ensuring a fully optimized RTL design before implementation handoff. This provides the physical design tools a strong starting point.

Intelligent RTL Debugging Assistant System

Joules RTL Design Studio further distinguishes itself with an intelligent RTL debugging assistant system. It provides early power, performance, area and congestion (PPAC) metrics and actionable debugging information throughout the design cycle‑including logical, physical, and production implementation stages. Engineers can thoroughly explore “what-if” scenarios and identify potential resolutions with ease. This not only saves valuable time but also improves the overall design outcomes, leading to more efficient chip designs.

Integrated AI Platform

A key highlight of this solution is its integration with Cadence Cerebrus, an AI-driven solution for design flow optimization, and the Cadence JedAI Platform, which facilitates big data analytics. By leveraging generative artificial intelligence (AI) for RTL design exploration and comprehensive analytics with Cadence’s leading AI portfolio, designers gain new insights into design space scenarios, floorplan optimization, and frequency versus voltage tradeoffs. This opens up new possibilities for creative exploration and significantly enhances design productivity.

The software’s capabilities are based on proven engines, shared with Cadence’s Innovus Implementation System, Genus Synthesis Solution, and Joules RTL Power Solution. This integration allows users to access all analysis and design exploration features from a single intuitive graphical user interface (GUI), ensuring an optimal QoR and a seamless design experience.

Incorporating lint checker integration, Joules RTL Design Studio empowers engineers to run lint checkers incrementally. This capability helps rule out data and setup issues upfront, effectively reducing errors and accelerating the design completion process. The unified cockpit experience offered by the software caters to the specific needs of RTL designers, providing physical design feedback, localization, and categorization of violations, bottleneck analysis, and cross-probing between RTL, schematic, and layout. This user-friendly interface streamlines the design workflow and fosters productivity.

Intelligent System Design

Joules RTL Design Studio plays a vital role in Cadence’s broader digital full flow. This integrated flow offers customers a faster path to design closure, ensuring efficient and successful chip design. The tool aligns well with Cadence’s Intelligent System Design strategy, empowering engineers to achieve excellence in system-on-chip (SoC) design.

Summary

The impact of this innovation extends to all aspects of physical design, from power and performance to area and congestion. By incorporating advanced technologies like machine learning, big data analytics, and generative artificial intelligence, Cadence has engineered a powerful solution that empowers designers to achieve optimized RTL designs faster with improved QoR.

Customers from various industries have endorsed its powerful capabilities and the benefits it brings to their design processes. For details, refer to the Joules RTL Design Studio press release.

For more information, visit the Joules RTL Design Studio product page.

Also Read:

Cadence and AI at #60DAC

Automated Code Review. Innovation in Verification

Xcelium Safety Certification Rounds Out Cadence Safety Solution

August 8, 2023August 22, 2023

DVCon India 2023 | Keynote: “Journeying Beyond AI: Unleashing the Art of Verification”

DVCon India 2023 | Keynote: “Journeying Beyond AI: Unleashing the Art of Verification”
by Daniel Nenni on 08-08-2023 at 10:00 am
Categories: Events, Maven Silicon, Semiconductor Services

DVCon India 2023 | Keynote: “Journeying Beyond AI: Unleashing the Art of Verification” by Sivakumar P R, Founder & CEO, Maven Silicon

Get Ready for an Epic Tech Odyssey with the keynote, ‘Journeying Beyond AI: Unleashing the Art of Verification’, by P. R. Sivakumar, Founder, and CEO, Maven Silicon.

The semiconductor industry is undergoing a transformative shift, embracing novel design methodologies and innovative flows to meet the demands of a rapidly evolving technological landscape. In this keynote address, we will explore how these advancements, such as AI-driven Electronic Design Automation (EDA), System of Chips (SoCs) utilizing Chiplets with UCIe, and cutting-edge 2.5D and 3D advanced packaging techniques, are revolutionizing chip production. This transformative journey positions the semiconductor industry to emerge as a trillion-dollar market by 2030, fueled by the creation of complex chips boasting trillions of transistors.

The rise of disruptive technologies, such as AI, cloud computing, and autonomous vehicles, has sparked a pressing need for sophisticated SoCs and chips specially designed to cater to these domains. These intricate designs incorporate standard CPUs, GPUs, FPGAs, and specialized AI accelerators, providing the foundation for groundbreaking innovation. With AI serving as a key driver for progress, its pervasive influence is permeating every industry sector.

Within the realm of EDA, machine learning has emerged as a vital tool, significantly enhancing the efficiency of the design and verification processes. Leveraging the power of machine learning, we are propelled towards the adoption of AI-driven EDA, facilitating the creation of advanced chips that fuel the growth and proliferation of emerging technologies. During this keynote, we will delve into the uncharted territory of verification challenges stemming from these new designs. Furthermore, we will illustrate how AI-driven EDA empowers verification engineers to efficiently validate these state-of-the-art chips, enabling them to unleash their creative potential and innovate with unprecedented freedom.

To know more, click here

About Maven Silicon
Maven Silicon is a trusted VLSI Training partner that helps organizations worldwide build and scale their VLSI teams. We provide outcome-based VLSI training with our variety of learning tracks i.e. RTL Design, ASIC Verification, DFT, Physical Design, RISC-V, and ARM etc. delivered through our cloud-based customized training solutions. To know more about us, visit our website.

Also Read:

Upskill Your Smart Soldiers and Conquer the Chip War in Style!

Chip War without Soldiers

Maven Silicon’s RISC-V Processor IP Verification Flow

August 8, 2023August 7, 2023

The Era of Flying Cars is Coming Soon

The Era of Flying Cars is Coming Soon
by Ahmed Banafa on 08-08-2023 at 6:00 am
Categories: Automotive
5 Comments

For decades, the concept of flying cars has captivated our imagination, fueling visions of a future where we can soar above the ground, free from the constraints of traffic and congestion. While once considered purely the stuff of science fiction, recent advancements in technology have brought us closer to turning this fantasy into a reality. Electric vertical takeoff and landing (eVTOL) vehicles, commonly known as flying cars, hold the promise of revolutionizing transportation, offering new levels of efficiency, convenience, and accessibility. It’s important to explore the needs driving the development of flying cars, the challenges they face, the benefits they offer, the risks involved, and what the future holds for this transformative technology.

Needs for Flying Cars

· Congestion and Traffic Woes: Growing urbanization and population density have led to increasingly congested roads in cities around the world. Commuting times have become longer, and frustration levels have risen. Flying cars could alleviate these problems by utilizing the airspace, bypassing traffic and reducing travel times. This could lead to more efficient transportation and improved overall mobility.

· Transportation Accessibility: Flying cars have the potential to address accessibility issues by providing transportation options for areas with limited infrastructure. Remote regions, islands, and disaster-stricken areas could benefit greatly from the ability to fly above ground-based obstacles, connecting previously isolated communities. Flying cars could bridge the gap between urban and rural areas, fostering economic development and social integration.

· Rapid Emergency Response: Flying cars could revolutionize emergency services by enabling faster response times and facilitating the transportation of medical supplies, organs for transplantation, and injured individuals to hospitals. In situations where time is critical, such as during natural disasters or in hard-to-reach locations, flying cars could make a significant difference in saving lives and minimizing the impact of emergencies.

Challenges of Flying Cars

· Infrastructure Requirements: The widespread implementation of flying cars requires the development of a comprehensive infrastructure framework. This includes establishing designated landing and takeoff zones, creating charging stations for electric vehicles, designing efficient air traffic management systems, and establishing regulations to ensure safe and efficient operations. Building this infrastructure will be a significant challenge that requires careful planning and coordination.

· Safety and Reliability: Ensuring the safety and reliability of flying cars is of paramount importance. New technologies, such as autonomous flight systems, collision avoidance mechanisms, and fail-safe protocols, must be developed and rigorously tested to minimize the risk of accidents and malfunctions. Safety standards and certifications will need to be established to instill public confidence in this emerging mode of transportation.

· Noise Pollution: Flying cars introduce the challenge of managing noise pollution in urban areas. The sound of numerous flying vehicles could disrupt the tranquility of residential neighborhoods and potentially cause annoyance or discomfort. Efforts must be made to design quieter propulsion systems and establish regulations to minimize noise emissions, ensuring that the benefits of flying cars do not come at the expense of quality of life for those on the ground.

Benefits of Flying Cars

· Efficient Urban Mobility: Flying cars have the potential to significantly reduce commuting times by bypassing congested roads. This could lead to increased productivity, improved work-life balance, and enhanced overall quality of life for urban dwellers. Imagine being able to travel across a crowded city in minutes instead of hours, with the freedom to avoid gridlock and traffic congestion.

· Environmental Sustainability: Electric-powered flying cars have the potential to contribute to environmental sustainability, provided they are powered by renewable energy sources. By shifting transportation from ground-based vehicles to the sky, flying cars could help reduce carbon emissions and mitigate the impacts of climate change. This transition to clean energy-powered transportation could have a positive impact on air quality and the overall health of our planet.

· Economic Opportunities: The development and deployment of flying cars can stimulate economic growth and create new job opportunities. Manufacturing flying cars, building and maintaining the necessary infrastructure, and managing air traffic control systems all require a skilled workforce. Additionally, new industries and services could emerge around flying car technology, further boosting local economies and fostering innovation.

Risks Associated with Flying Cars

· Air Traffic Management: The integration of flying cars into existing airspace systems poses significant challenges in terms of air traffic management. Ensuring the safe coexistence of conventional aircraft, drones, and flying cars requires the development of robust communication and navigation systems. Cooperation between aviation authorities, technology providers, and regulators is crucial to establishing effective protocols and infrastructure to manage the complex airspace environment.

· Cybersecurity: As flying cars become increasingly reliant on software and connectivity, the risk of cybersecurity threats arises. Safeguarding against hacking, system breaches, and data privacy breaches is crucial to ensure passenger safety and protect against potential malicious activities. Strong cybersecurity measures and protocols must be implemented to ensure the integrity and privacy of the systems controlling flying cars.

· Regulatory Framework: The development of comprehensive regulations and policies is essential to govern the use of flying cars. Striking a balance between innovation and safety, while addressing concerns related to privacy, noise pollution, and liability, requires careful consideration. Governments and regulatory bodies need to collaborate with industry stakeholders to establish a robust regulatory framework that ensures the safe and responsible deployment of flying car technology.

Future Outlook

· Technology Advancements: Ongoing advancements in electric propulsion, battery technology, autonomous systems, and materials science will contribute to improving the performance, safety, and affordability of flying cars. Continued research and development will likely lead to more efficient and environmentally friendly flying car models in the future.

· Urban Air Mobility Ecosystems: The successful integration of flying cars will involve the creation of urban air mobility ecosystems. This will require collaboration between vehicle manufacturers, infrastructure developers, air traffic control authorities, policymakers, and communities. Establishing a robust framework that encompasses infrastructure, regulations, and public acceptance is essential for the widespread adoption and safe operation of flying cars.

· Public Acceptance: Public acceptance is critical for the successful integration of flying cars into society. Transparency in terms of safety, privacy, and environmental impact will play a vital role in fostering public confidence in this revolutionary mode of transportation. Educating the public about the benefits and addressing concerns through effective communication and public engagement initiatives will be crucial for the widespread acceptance and adoption of flying cars.

Flying cars hold the potential to transform transportation and reshape our urban environments. By addressing the needs for efficient mobility, accessibility, and emergency response, flying cars offer promising solutions to the challenges faced by our current transportation systems. However, significant hurdles related to infrastructure development, safety, and regulation must be overcome. With careful management of risks and continued technological advancements, flying cars could usher in a new era of transportation that is efficient, sustainable, and accessible to all. The future of flying cars depends on collaboration between industry, government, and society as we work together to turn this futuristic vision into a tangible reality.

Ahmed Banafa’s books

Covering: IoT, Blockchain and Quantum Computing

Also Read:

Xcelium Safety Certification Rounds Out Cadence Safety Solution

Sondrel Extends ASIC Turnkey Design to Supply Services From Europe to US

Automotive IP Certification

August 7, 2023September 22, 2023

Cadence and AI at #60DAC

Cadence and AI at #60DAC
by Daniel Payne on 08-07-2023 at 10:00 am
Categories: Cadence, EDA

Paul Cunningham from Cadence presented at the #60DAC Pavilion and gave one of the most optimistic visions of AI applied to EDA that I’ve witnessed, so hopefully I can convey some of his enthusiasm and outright excitement in my blog report. Mr. Cunningham reviewed the various ages of EDA design with each era providing about a 10X productivity improvement: Transistor-level, cell-based, RTL reuse, AI-driven system design.

Paul Cunningham, Cadence

Human chip designers are good at intuition, judgement, remembering experiences and understanding context, however, we are limited in our serial thinking patterns. AI, on the other hand has merits like scalability, parallelization, access to massive data, and the ability to classify data. To reach the next 10X productivity improvement will take an approach that accelerates design efficiency by keeping the human in the loop, not really replacing engineers.

In EDA 1.0, there were all of these separate EDA tools, each with their own silo of data, and most of the time was spent waiting to get back tool results so that an engineer could analyze the results. Now, with EDA 2.0, all of the tool results get collected as big data, then cataloged and indexed, creating a more wholistic viewpoint on the design process.

Within Cadence the data platform is called JedAI—Joint Enterprise Data and AI Platform—which lets engineering teams visualize workflow and design data across some of their tools, so expect it to grow across all of their tools in the future. Another use of AI at Cadence is in running the combination of logic synthesis and P&R tools to achieve better PPA results, and that’s called Cerebrus. In just a short period of time, Cerebrus has been used on more than 180 tapeouts, and using this methodology allows one engineer to do the work of 10 previous engineers, so that’s a big productivity boost and allows engineers to focus on more strategic projects.

On the PCB tool side, the application of AI is called Allegro X AI, and there, engineers are seeing 30-50X improvements on placement and routing, while achieving better QoR.

Functional verification is another hot topic area to apply AI, and the basic question remains, “Is verification ever done?” Verification engineers still need to debug why a test just failed, and why the coverage goals not being reached. AI technology can help by creating a triage funnel, and answering basic questions like, “Who just checked in recent changes?” AI is used to rank bug locations and help pinpoint which change caused the latest failures. Cadence has also found that applying language processing on waveforms is better done by machine in terms of finding patterns and signatures of failures. The product name for AI applied to verification is called Verisium.

In general, AI can be applied to most NP-complete problems in computer science. Using constraint-solving in randomization also shows promise with AI technique, as AI can learn what was randomized before, so you are not starting all over again. The Xcelium logic simulator uses ML to get up to 5X faster coverage with the same CPU usage as previous approaches.

For formal logic verification, the Jasper apps have a method where AI guides and helps choose the best proof techniques and can create about 30% more properties versus a manual approach.

Summary

At Cadence, the product groups have been adding AI capabilities to help IC, PCB designers and verification engineers become more productive, explore more alternatives, and even improve the quality of results. Yes, a human engineer still has to direct the EDA tools and choose the best results to meet their specific PPA, DFT and DFM goals. The first application of AI is in digital flows where models are trained at the customer site—they don’t get shipped pre-trained.

Cadence has applied AI techniques successfully across many of their tools, so I look forward to more announcements to come.

Market Detail

Forecast Summary

Market Outlook

Also Read:

A Look Back: The State of the Japanese Semiconductor Industry

The New Landscape: Attracting TSMC and Rebuilding the Foundry Sector

The Rise of Rapidus: A Bold Leap Forward

Conclusion: From Mirage to Reality, A Blueprint for Others?

Sources:

Also Read:

The verification objective

QED

Combining formal methods and QED

Also Read:

Software and DevOps

What about hardware design?

Cloud

Interest in unifying hardware and software DevOps

Actionable Intelligence

Intelligent RTL Debugging Assistant System

Integrated AI Platform

Intelligent System Design

Summary

Also Read:

Also Read:

Also Read:

Summary

Related Blogs