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Cadence and AI at #60DAC

Cadence and AI at #60DAC
by Daniel Payne on 08-07-2023 at 10:00 am

Paul Cunningham from Cadence presented at the #60DAC Pavilion and gave one of the most optimistic visions of AI applied to EDA that I’ve witnessed, so hopefully I can convey some of his enthusiasm and outright excitement in my blog report. Mr. Cunningham reviewed the various ages of EDA design with each era providing about a 10X productivity improvement: Transistor-level, cell-based, RTL reuse, AI-driven system design.

Cadence, AI, #60DAC min
Paul Cunningham, Cadence

Human chip designers are good at intuition, judgement, remembering experiences and understanding context, however, we are limited in our serial thinking patterns. AI, on the other hand has merits like scalability, parallelization, access to massive data, and the ability to classify data. To reach the next 10X productivity improvement will take an approach that accelerates design efficiency by keeping the human in the loop, not really replacing engineers.

In EDA 1.0, there were all of these separate EDA tools, each with their own silo of data, and most of the time was spent waiting to get back tool results so that an engineer could analyze the results. Now, with EDA 2.0, all of the tool results get collected as big data, then cataloged and indexed, creating a more wholistic viewpoint on the design process.

Within Cadence the data platform is called JedAI—Joint Enterprise Data and AI Platform—which lets engineering teams visualize workflow and design data across some of their tools, so expect it to grow across all of their tools in the future. Another use of AI at Cadence is in running the combination of logic synthesis and P&R tools to achieve better PPA results, and that’s called Cerebrus. In just a short period of time, Cerebrus has been used on more than 180 tapeouts, and using this methodology allows one engineer to do the work of 10 previous engineers, so that’s a big productivity boost and allows engineers to focus on more strategic projects.

On the PCB tool side, the application of AI is called Allegro X AI, and there, engineers are seeing 30-50X improvements on placement and routing, while achieving better QoR.

Functional verification is another hot topic area to apply AI, and the basic question remains, “Is verification ever done?” Verification engineers still need to debug why a test just failed, and why the coverage goals not being reached. AI technology can help by creating a triage funnel, and answering basic questions like, “Who just checked in recent changes?” AI is used to rank bug locations and help pinpoint which change caused the latest failures. Cadence has also found that applying language processing on waveforms is better done by machine in terms of finding patterns and signatures of failures. The product name for AI applied to verification is called Verisium.

In general, AI can be applied to most NP-complete problems in computer science. Using constraint-solving in randomization also shows promise with AI technique, as AI can learn what was randomized before, so you are not starting all over again. The Xcelium logic simulator uses ML to get up to 5X faster coverage with the same CPU usage as previous approaches.

For formal logic verification, the Jasper apps have a method where AI guides and helps choose the best proof techniques and can create about 30% more properties versus a manual approach.

Summary

At Cadence, the product groups have been adding AI capabilities to help IC, PCB designers and verification engineers  become more productive, explore more alternatives, and even improve the quality of results. Yes, a human engineer still has to direct the EDA tools and choose the best results to meet their specific PPA, DFT and DFM goals. The first application of AI is in digital flows where models are trained at the customer site—they don’t get shipped pre-trained.

Cadence has applied AI techniques successfully across many of their tools, so I look forward to more announcements to come.

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