Crack the Verification Double Trouble!
Register for CadenceTECHTALK to find out how to achieve verification closure with the same coverage with up to a 10X reduction in simulation cycles.
Chips are becoming bigger and more complex, adding to already existing verification woes. Design and verification engineers struggle with… Read More
Don’t let power-related issues that appear late in the verification cycle impact your project schedule. Register for a webinar that shows you how to catch low-power issues early on.
The Cadence low-power solution considers power at every step of the design flow, from architecture to functional verification, analysis, implementation,… Read More
Register for CadenceTECHTALK to find out how to achieve verification closure with the same coverage with up to a 10X reduction in simulation cycles.
Chips are becoming bigger and more complex, adding to already existing verification woes. Design and verification engineers struggle with running billions of regression cycles… Read More
Date: Tuesday, December 13, 2022
Time: 09:00 GMT / 10:00 CET / 11:00 EET & Israel / 14:30 IST
Simulator performance is critical owing to the exponentially increasing complexity of SoC designs and shrinking market time. Cadence® Xcelium™ is a leader in simulation performance, and we focus relentlessly on improving the core… Read More
Machine learning (ML) is finding its way into many of the tools in silicon design flows, to shorten run times and improve the quality of results. Logic simulation seemed an obvious target for ML, though resisted apparent benefits for a while. I suspect this was because we all assumed the obvious application should be to use ML to refine… Read More
Date: Wednesday, September 21, 2022
Time: 9:00am – 10:00am PDT
Register for this CadenceTECHTALK if you are looking for an end-to-end solution for all your verification requirements in automotive, mobile, and hyperscale designs.
This CadenceTECHTALK introduces Xcelium Apps, a portfolio of domain-specific technologies… Read More
