Are you ready to lead the way in gate-level digital simulations (GLS)? Dive into Cadence’s exclusive webinar and uncover the revolutionary Xcelium Multi-Core (MC) App—a game changer for GLS, allowing you to parallelize and expedite simulations like never before.
What You’ll Gain:
Insight: Understand why the Xcelium… Read More
Date and time: Thursday, September 7, 13:00-14:15
Organizer:
Cadence Design Systems Japan
Innotech Co., Ltd. IC Solution Division
Cost: Free
Venue: Online (Zoom webinar)
*It is also possible to participate from a web browser.
We recommend using Google Chrome, Firefox, or Chromium Edge.
Registration deadline: Wednesday, … Read More
Paul Cunningham from Cadence presented at the #60DAC Pavilion and gave one of the most optimistic visions of AI applied to EDA that I’ve witnessed, so hopefully I can convey some of his enthusiasm and outright excitement in my blog report. Mr. Cunningham reviewed the various ages of EDA design with each era providing about… Read More
Date: Wednesday, June 7, 2023
Time: 11:00 am PDT | 2:00 pm ET | 8:00 pm CEST
Xcelium mixed-signal simulation enables teams to achieve digital simulation speeds of analog models and opens mixed-signal designs to advanced verification techniques typically applied within standard verification flows. Built on a SystemVerilog… Read More
Date: Wednesday, June 7, 2023
Time: 11:00 am PDT | 2:00 pm ET | 8:00 pm CEST
Xcelium mixed-signal simulation enables teams to achieve digital simulation speeds of analog models and opens mixed-signal designs to advanced verification techniques typically applied within standard verification flows. Built on a SystemVerilog… Read More
Crack the Verification Double Trouble!
Register for CadenceTECHTALK to find out how to achieve verification closure with the same coverage with up to a 10X reduction in simulation cycles.
Chips are becoming bigger and more complex, adding to already existing verification woes. Design and verification engineers struggle with… Read More
Don’t let power-related issues that appear late in the verification cycle impact your project schedule. Register for a webinar that shows you how to catch low-power issues early on.
The Cadence low-power solution considers power at every step of the design flow, from architecture to functional verification, analysis, implementation,… Read More
Register for CadenceTECHTALK to find out how to achieve verification closure with the same coverage with up to a 10X reduction in simulation cycles.
Chips are becoming bigger and more complex, adding to already existing verification woes. Design and verification engineers struggle with running billions of regression cycles… Read More
Date: Tuesday, December 13, 2022
Time: 09:00 GMT / 10:00 CET / 11:00 EET & Israel / 14:30 IST
Simulator performance is critical owing to the exponentially increasing complexity of SoC designs and shrinking market time. Cadence® Xcelium™ is a leader in simulation performance, and we focus relentlessly on improving the core… Read More
