SemiWiki – Page 177 – The Open Forum for Semiconductor Professionals

July 6, 2022July 21, 2022

Accellera Update: CDC, Safety and AMS

Accellera Update: CDC, Safety and AMS
by Bernard Murphy on 07-06-2022 at 6:00 am
Categories: Accellera, Automotive, Semiconductor Services

I recently had an update from Lu Dai, Chairman of Accellera, also Sr. Director of Engineering at Qualcomm. He’s always a pleasure to talk to, in this instance giving me a capsule summary of status in 3 areas that interested me: CDC, Functional Safety and AMS. I will start with CDC, a new proposed working group in Accellera. To manage hierarchical CDC analysis back in my Atrenta days, you would first analyze a block, then use that analysis to define pseudo constraints on ports of the block, and so on up through the hierarchy. These pseudo constraints might capture things like internal input or output synchronization with related clock info. Sort of a CDC-centric abstraction of the block.

We should have guessed that other tool providers would do something similar, with their own constraint extensions. Which creates a problem when using IP from multiple vendors, each of whom use their own tools for CDC. Maybe you would have to re-do the analysis from scratch for a block? Which may not be possible for encrypted RTL. This is an obvious candidate for standardization – defining abstractions in a common language. SDC-based, no doubt, since these constraints must intermingle with the usual input, output and clock constraints. A worthy effort in support of CDC verification teams.

Functional Safety

It might seem that ISO 26262 is the final word in defining functional safety (FuSa) requirements for electronic design for vehicles. In fact, like most ISO standards ISO 26262 is more about process than detailed guidelines. As tools, IPs and Systems development have advanced to comply with FuSa needs it has become obvious that we need more rigor in those expectations. Take a simple example. What columns should appear in an FMEDA table, in what order and with what headings? Or could this information be scripted instead? None of this is nailed down by ISO 26262. Formats/scripting approaches are completely unconstrained, creating a potential nightmare for integrators.

More generally, there is a need to ensure standardized interoperability in creating and exchanging FuSa information between suppliers and integrators. Which should in turn encourage more automation. So when I claim my IP meets some safety goal, you don’t just have to take my word for it. You can run your own independent checks. On a related note, the methodology should support traceability (a favorite topic of mine). Allowing for validation across the development lifecycle, from IPs to cars. Incidentally there is a nice intro to Accellera work in this area from DAC 2021.

Lu mentioned a related effort in IEEE. I believe this is IEEE P2851, looking at some fairly closely related topics. Lu tells me the Accellera and IEEE groups have had a number of discussions to ensure they won’t trip over each other. His quick and dirty summary is that Accellera is handling the low-level tool and format details while IEEE is aiming somewhat higher. I’m sure that eventually the two efforts will be merged in some manner.

UVM-AMS

The stated objective of this working group is to standardize a method to drive and monitor analog/mixed-signal nets within UVM. Also to define a framework for the creation of analog/mixed-signal verification components by introducing extensions to digital-centric verification IP.

In talking with Lu, the initial objective is to align with existing AMS efforts, in Verilog, SystemVerilog and SystemC. There’s a nice background to the complexities of AMS modeling in simulation HERE for those of us who might have thought this should be easy to solve. Even the basics of real number modeling are still not frozen. Analog signals are not just continuous variants of digital signals; think of the complex number representations common in RF. So there’s history and learning which the standard should leverage yet not disrupt unnecessarily.

AMS teams want the benefits of UVM methodologies, but they don’t want to start from scratch. Aligning those benefits with existing AMS requirements is the current focus. Lu says that many of these requirements aren’t language specific. The working group is figuring out the semantics of the methodology first, then will look more closely at syntax issues.

Accellera will be presenting more on this topic at DAC 2022 so you’ll have an opportunity to learn more there.

July 5, 2022July 6, 2022

Jade Design Automation’s Register Management Tool

Jade Design Automation’s Register Management Tool
by Kalar Rajendiran on 07-05-2022 at 10:00 am
Categories: EDA, Events, Jade Design Automation

When more than one person is working on any project, coordination is imperative. When the team size grows, being in sync becomes essential. When it comes to SoC design management, registers and bit fields are used to communicate status of results and execute conditional controls. The Register Management function plays an essential role during the course of any modern day SoC product development. Earlier this year, SemiWiki introduced Jade Design Automation (JadeDA) to its readership, through an interview with its CEO and Founder, Tamas Olaszi. JadeDA is focused on register management of a chip design starting from the system architecture stage all the way to software bring-up.

This post will discuss register management and a feature to configure RISC-V processor registers. JadeDA will be showcasing their Register Manager tool at the upcoming DAC 2022 in San Francisco. I had an opportunity to chat with Tamas and this blog is based on that conversation.

Register Management Benefits

Where

While register management has always been important on any chip design project, it takes more importance in today’s world of hardware/software co-design/co-development. Even an average complexity chip could include 100,000 or even millions of registers. During the design phase, bit fields in those registers could be change frequently, even many times in a day. This necessitates the validation, regeneration of RTL, updating of UVMs and the relevant documentation in close to real-time as possible. Without register management, different teams could be out-of-sync. For example, a change made by the design team may not be noticed by the verification team right away. The software team may be working off of outdated information, wasting cycles on developing code that would need to be changed.

Following is a real life example that Tamas narrated during our chat. It was an embedded software development project. The documentation the team was working off of said to set certain bits and then wait for certain things to happen and then perform some actions. The hardware team knew when that something happens because they have access to an internal register. But the software team doesn’t have access to this register. No status bits or interrupts were triggered. Without knowing, the software could be waiting forever to take action. This is the kind of thing that can happen if there is no centralized information access that all teams could review, verify and work from.

While the above example is from an embedded real-time device application, the same goes for any device including HPC-oriented high-performance application. Only difference is, we can expect even more frequent updates the larger and more complex a design gets. And the speed at which the centralized information gets updated and all relevant code and documentation gets regenerated becomes critical.

Who

A good register management capability will render the following functional roles the respective benefits. It also allows automated broadcast of updated information to all the different teams working on a project.

System architects can capture and maintain all the high level system information in a centralized way.
System Integrators can pull together IPs from various sources to a centralized platform for enhanced quality.
IP teams can auto-generate production ready RTL and UVM register descriptions throughout the development process, which is a great productivity booster.
Engineering Managers can monitor the consistent and high quality release deliverables offered to their internal or external customers.
Software Engineers can have register information loaded into their debuggers so they can instantly see what register they are working with on a particular offset; they can do this without having to wade through pages of documentation.

JadeDA’s Register Management Tool

JadeDA has kept it simple and straightforward by naming their register management tool, the Register Manager. The tool efficiently manages all tasks around the HW/SW interface of an SoC. Users can capture register and bitfield information at the IP level as well as the memory maps on the IP, subsystem and SoC level. The Register Manager generates RTL, Verification, SW, Documentation and data Interoperability formats like IP-XACT 1685-2009 and 1685-2014 from these descriptions.

Data Model and Flexibility for Customization

While data models can be based off of standards such as IP-XACT and SystemRDL, standards evolve very slowly. A proprietary data model from a supplier with strong support for customization serves customers well. JadeDA’s importing tools can migrate IP-XACT and SystemRDL based data models. Data models/tools based off of IP-XACT usually have vendor extensions. JadeDA tool’s data model is richer than what IP-XACT offers. Legacy data in custom formats can be imported via the tool’s API. The API is very efficient and well documented. JadeDA can also easily import register information stored in excel sheets.

GUI

The Register Manager has a rich and intuitive GUI to visualize and edit the HW/SW interface and edit the register and bitfield information. The GUI is much more than just entry fields for various attributes. It can be controlled with mouse only to change attributes like offsets, widths, access types and reset values. There is also a full keyboard support with intuitive focus traversal that allows quick and efficient data capture without raising the hand from the keyboard. Typing pre-existing information from a PDF document can be done without having to reach for the mouse in-between keyboard entries. This is a productivity enhancement.

Note: The tool also has a fully functional shell mode for power users as well as fully scriptable command files for automated flows.

Performance

As changes happen in a design, the tool can capture the data, validate it and generate RTL, UVM, documentation, software and IP-XACT collateral in a few seconds. Jade DA has noticed that its tool runs in an order of magnitude less time than what is available in the marketplace today. And the performance of JadeDA tool scales linearly.

Processor Registers Configurability Feature

JadeDA will be showcasing this new feature of the Register Manager tool at DAC 2022.

JadeDA can deliver its customers the superset of control and status registers (CSRs) through the tool’s GUI. As the customers configure their designs, they can get rid of the CSRs they don’t need for a particular design. A RISC-V based design serves as a good case study. The RISC-V specification offers a whole bunch of CSRs, not all of which are used by all customers. And different customers or different projects at the same customer may use different selection of CSRs. The tool captures all of the registers in all the details contained in the RISC-V specification. With the configurability feature, users can configure the particular subset they need. Some of the configuration options are available as RTL configurable parameters. If the customer turn them off, the users won’t be able to configure the corresponding registers.

This configurability feature is something that JadeDA can implement in its tool for any processor architecture/ISA. Contact JadeDA to explore.

You have to see the live demo to fully appreciate the power of the tool, the user interface and ease of use. See the Register Manager Tool Demo @Booth Number 2430 at DAC 2022 in San Francisco.

Meanwhile, here are some screenshots from the tool. The following two Figures show the scenarios of when a FPU and corresponding registers are included in the configuration and when they are not.

The following Table shows the supervisor related CSRs found in the RISC-V specification.

The following relates to a case of an application processor where supervisor related CSRs are needed. The screenshot below shows their conditional presence being enabled.

See the Register Manager Tool Demo @Booth Number 2430 at DAC 2022 in San Francisco.

July 5, 2022December 27, 2023

5G for IoT Gets Closer

5G for IoT Gets Closer
by Bernard Murphy on 07-05-2022 at 6:00 am
Categories: 5G, Ceva, IoT, IP

Very recently, 3GPP announced that 5G Release 17 was finalized. One important consequence is that 5G RedCap (reduced capacity) is now real and that means 5G becomes accessible to IoT devices. Think smart wearables (e.g. watches), industrial sensors and surveillance devices. “So what?”, you protest. “I don’t need 5G on my watch. It can link to my phone over Bluetooth and let the phone handle 5G communication.” Yes it can, but have you ever wondered why you always need your phone to use your watch?

That seems like a half-step to convenience, a nice light device on your wrist tethered to an increasingly bulky device in your pocket. When you’re jogging, hiking, working out, wouldn’t it be nice to only need the watch? Industrial sensors and surveillance devices rely more on Wi-Fi for communication but what if the Wi-Fi isn’t very good, or non-existent? Is it time to cut the cord and let these devices talk directly to the cellular network?

The real growth in 5G

The smartphone market is already slowing according to multiple surveys. 5G may generate a boost in support of mobile gaming and high-quality streaming but still the heady growth of early years seems unlikely to re-emerge. That’s why IoT applications have become so interesting. The total available market is not bounded by human users, only by applications. Millions of smart parking meters, moisture sensors in field, bridge stress sensors, power grid sensors, etc, etc. Analysts estimate 1.24 billion M2M non-handset devices shipping in 2027. Smart watch volume estimates show up to 230 million units by 2026, making them an encouraging consumer option to pick up from declining volumes in smart phones. There doesn’t seem to be a killer app here. Volumes are projected to be roughly divided between public sector infrastructure, smart metering, consumer electronics, intelligent buildings, security, retail and commerce, healthcare and transport and logistics.

What underlines the strength of this opportunity is that 5G infrastructure build-out is already underway. Not as fast as we’d like, and it may be a financial challenge for the mobile network providers but coming. There has been talk of expanding the reach of Bluetooth (mesh networks) and Wi-Fi (Wi-Fi 6). Technologically these are possible, but someone must pay for building wide coverage infrastructure. Which seems unlikely given existing investment in 5G infrastructure. Moreover, it’s difficult to beat cellular reach for remote applications – agriculture, highways, power grids, etc.. 5G RedCap is increasingly looking like the best fit for IoT communication.

PentaG2-Lite Well Positioned to Help

As the only 5G NR IP platform on the market, CEVA’s PentaG2 is compelling solution for those needing an embedded solution to meet cost and power goals. This will particularly be true for IoT builders who are likely to see a good fit in the PentaG2-Lite version. This IP offers a wide range of accelerators for modem and other functions. First product shipments probably will appear 2025, but that date requires builders to start planning now. CEVA offers an integrated SystemC simulation environment for architects in support of that early design.

You can learn more by watching this webinar.

July 4, 2022July 6, 2022

Using AI in EDA for Multidisciplinary Design Analysis and Optimization

Using AI in EDA for Multidisciplinary Design Analysis and Optimization
by Daniel Payne on 07-04-2022 at 10:00 am
Categories: Cadence, EDA

Most IC and system engineers follow a familiar process when designing a new product: create a model, use parameters for the model, simulate the model, observe the results, compare results versus requirements, change the parameters or model and repeat until satisfied or it’s time to tape out. On the EDA side, most tools perform some narrow function in a single domain, and it’s up to the EDA user to control the tool, read the results, and then iterate while manually optimizing.

In the late 1980’s we saw the birth of smarter EDA tools like logic synthesis, which at first only optimized a gate level netlist into a reduced form, then later accepted RTL language and produced an optimized, process-specific, gate-level netlist. By the mid 2000’s there was an application of Machine Learning (ML) to Monte Carlo simulations for SPICE simulators, saving circuit designers time and effort. Recently, even Google has applied ML to produce better placement results for large SoC designs than what a human can produce. The trends have been clear, EDA tool developers have created smarter tools, but mostly limited to single domains, like: Logic design, SPICE and floor planning.

On June 7 some big news in EDA came from Cadence, as they announced something called Optimally Intelligent System Explorer, an AI-based approach for Multidisciplinary Design Analysis and Optimization (MDAO). The days of separated silos of EDA tools operating in only one domain are changing into more complex, multi-domain tools. Cadence has gone so far as to organize a Multi-Physics System Analysis Group, where Ben Gu is the Vice President. The new product name isOptimality Explorer, and it works across three system-level EDA tools:

Clarity – 3D Electromagnetic (EM) field solver
Sigrity X – Distributed simulation for signal and power integrity (SI/PI)
Celsius – Thermal solver (Optimality integration coming soon)

Optimality Explorer

The diagram above shows a system design where a communication channel consists of an IC driver, package, PCB layout, package, and finally a receiver inside the final IC. Criteria for success is optimizing the physical layouts to ensure an acceptable return and insertion loss, while managing cross-talk issues and maintaining signal isolation. Optimality Explorer is used to automatically guide optimization, using both the Clarity and Sigrity X tools, and it decides what to change for each tool run, and figure out when an optimal solution has been found.

For example, the system designer specifies that return loss has to be lower than some threshold, and then Optimality Explorer reads from Allegro, creates design variables, controls the optimization process, and finds the optimum solution. Here’s a plot from an optimization run where the criteria was a return loss under -35dB:

Optimization Results: Return Loss

The blue dots each represent an iteration during optimization, and the red line is the progress towards reaching the design goal. This automated method for optimization happens much faster than the manual approaches used for the past decades. Cadence is claiming a 10X faster time to optimization by using Optimality.

The theory of applying ML to optimization sounds good, but what about real world results? Great question. At DesignCon there was a presentation by Kyle Chen of Microsoft, where they used Optimality to optimize micro-stacked vias in a rigid-flex PCB. Kyle wrote, “As an early adopter of the Cadence Optimality Intelligent System Explorer, we stressed its performance on a rigid-flex PCB with multiple via structures and transmission lines. The Optimality Explorer’s AI-driven optimization allowed us to uncover novel designs and methodologies that we would not have achieved otherwise. Optimality Explorer adds intelligence to the powerful Clarity 3D Solver, letting us meet our performance target with accelerated efficiency.”

Micro-Stacked Vias

This approach may sound familiar to Cadence IC designer users in the RTL to GDS flow, because last year they announced Cerebrus, an AI approach using ML to explore the design space for Power, Performance and Area (PPA) through placement, routing and timing closure. The same kind of reinforcement ML in Cerebrus has also been used in Optimality Explorer.

Summary

EDA tools have been used to create every AI chip every designed, and now AI and specifically ML is being applied to EDA tools like Optimality Explorer, to explore the design space of systems by optimizing more quickly than manual methods. The first two tools from Cadence that work with Optimality Explorer are Sigrity X and Clarity, then expect Celsius to be the next tool added. Multi-physics EDA, or multidisciplinary design analysis and optimization (MDAO) has begun in earnest.

Related Blogs

July 4, 2022July 19, 2022

Verifying Inter-Chiplet Communication

Verifying Inter-Chiplet Communication
by Daniel Nenni on 07-04-2022 at 6:00 am
Categories: Avery Design Systems, Chiplet, IP

Chiplets are hot now as a way to extend Moore’s Law, dividing functionality across multiple die within a single package. It’s no longer practical to jam all functionality onto a single die in the very latest processes, exceeding reticle limits in some cases and in others straining cost/yield. This is not an academic concern. Already server processors, FPGAs and large AI training platforms run to multiple chiplets on a die. The breakthrough in expanding functional design to chiplets serves not only growing gate counts in large systems. It also allows many functions can be parceled out to individual die at less aggressive technologies for lower cost and potentially broader availability. Reserving the most aggressive processes only for functions/die needing that advantage.

This seems like the best of all possible worlds, but the idea only works if you have a very fast (and low power) interconnect between those chiplets. That’s the goal of the Universal Chiplet Interconnect Express (UCIe). How do you verify compliance with a standard that is new in town? You must work with a company that has a track record in tight relationships with standard developers, in delivering VIP and compliance checking. Avery has that track record.

The foundations of UCIe

UCIe builds on well proven standards, particularly PCIe as a host extension interface, already long established in the PC and server world. Add to this CXL for coherent memory connectivity (memory, IO and cache) between chiplets. PCIe and CXL are mapped natively in UCIe in acknowledgement of the reality that they are already widely used. The fact that they plug-and-play with existing software is another not inconsiderable detail. Add this support for a raw streaming protocol as a way to extend to further protocols. Together, this combination seems like a no-brainer for chiplet-to-chiplet communication. I’ve heard some grumbling from the AI training world about the PCIe overhead impeding coherent communication performance with the core. Perhaps the streaming protocol might mitigate this issue. But anyway, for everyone else the benefits outweigh that bleeding edge limitation.

Thanks to short signal paths on substrate or interposer (for example), IO performance is expected to be 20x better than conventional PCIe SERDES, also at significantly lower power. The standard is also designed to support off-package connectivity, at board, rack or pod level, supported by retimers as needed. Scaling out is clearly a longer term goal.

High performance at low power and building on established standards. It is easy to see why UCIe has garnered wide support – from Intel (or course), also AMD, Google Cloud, Meta, Microsoft, Arm, Samsung, Qualcomm, TSMC and others.

Verification

A standard depends on tooling to verify compliance with the standard. I can’t speak to aspects of physical compliance checking but I do know that Avery is a contributing member and has built a VIP to validate functional compliance at the protocol and logical PHY layers. As an established provider of VIPs across multiple domains – high speed IO, storage, embedded storage, mobile, memory and others – Avery already has the chops to deliver for UCIe. Their PCIe and CXL VIPs are proven and their QEMU co-simulation platform simplifies software co-design and validation with RTL design.

Avery offers a complete functional verification platform based on its robustly tested verification IP (VIP) portfolio that enables pre-silicon validation of design elements. Its UCIe offering supports standalone UCIe die to die adapter and LogPHY verification along with integrated PCIe and CXL VIP to run over the UCIe stack. In addition to UCIe models it provides comprehensive protocol checkers, coverage, reference testbenches, and compliance test-suites utilizing a flexible and open architecture.

You can learn more HERE.

A Crisis in Engineering Education – Where are the Microelectronics Engineers?

A Crisis in Engineering Education – Where are the Microelectronics Engineers?
by Tom Dillinger on 07-03-2022 at 10:00 am
Categories: Events
24 Comments

At the recent VLSI Symposium on Technology and Circuits, a panel discussion presented a jarring forecast. The theme of the panel was “Building the 2030 Workforce: How to Attract Great Students and What to Teach Them?”, with participants from academia and industry, as well as a packed (and vocal) audience.

On the one hand, the forecasts for economic growth in the microelectronics industry are uniformly robust – “a $1T industry by 2030” (notwithstanding a short-term more muted outlook).

Yet, the clear message from all the panel participants was “Where will the microelectronics engineers necessary to support this growth come from?”

The figure below says it all. The disparity in college enrollment for EE versus CS majors continues to grow. (from Raja Koduri, Executive Vice President and general manager of the Accelerated Computing Systems and Graphics Group at Intel)

The goal of the panel session was to solicit ideas to address the issue. As you might imagine, there were conflicting opinions on the merits of some of the proposals put forth.

The goal of this article is the same, to solicit recommendations from SemiWiki readers on how to get more students interested in microelectronics.

“Show me the money”

One topic of discussion was the salaries offered to graduating software developers versus microelectronics engineers.

- “Students hear about software grads getting tremendous starting salaries. Why should they choose hardware engineering?”
- “It is simply not viable for us to pay entry-level engineers on large hardware teams that kind of money.”
- “When interviewing candidates, I look for a sense of passion about microelectronics. If their sole focus is money, it’s not a fit.”

Question: How could industry professionals and academics help generate that passion in students?

Academic + Government + Industry partnerships

“Other countries have recognized this issue, and have established special university programs for microelectronics students – from tuition incentives to assistance finding employment when they finish the program.”

Here’s a site with some examples – link.

“The American Semiconductor Academy Initiative is working on this issue in the U.S., a partnership between universities and SEMI.” – link.

Questions: How can academic/industry collaborations be more effective? What should be the role of government in addressing the microelectronics engineering shortage – should the U.S. follow the examples of other countries?

The Microelectronics EE Curriculum

The audience did not have clear opinions when posed with the question whether the current undergraduate EE curriculum was appropriate or needed revision to encourage more microelectronics students.

A passionate faculty member said, “I am one of a group of faculty that teach a tapeout course. It’s demanding, both on the students and the faculty. The cost per student to the university is high. Yet, the students say they benefit greatly from the experience. They learn about engineering projects, schedules, teamwork, and how tradeoffs need to be addressed.” (link, link, link)

I intend to follow-up further with the faculty, to see how this experience might scale to attract more students.

Questions: Is the microelectronics curriculum optimum? How do we educate students about the breadth of skills that are part of the microelectronics industry, to see what might ignite their passion (perhaps like a tapeout course)? Would high school be appropriate to introduce (STEM) students to a microelectronics curriculum?

Internships

“Offer more internships to EE students early in their studies, to get them industry exposure and excited about microelectronics.”

“Internships are hit-and-miss. Too often, there is just not a good fit with a student’s early background and our project opportunities. It’s a mismatch for both the student and the mentor. Instead of a positive experience, it turns into a negative.”

Questions: Is early industry internship experience worth the investment, to attract more students? How can the experience be more beneficial to both the student and the company?

The First Job Experience

“We often direct new hires into verification tasks to start their careers. And, we have let verification – one of the most exciting and vital roles on the team – come to be regarded as unappealing. We need to change perceptions about the importance of all the different facets of microelectronics, and make the first job a more valuable experience.”

Much of the panel discussion centered on providing (circuits and/or system) design coursework to students, and how that often differs from their initial job assignments. There was not much focus on how to expose students to other aspects that might appeal to them, areas like: product testing and bring-up; product qualification; sustaining product engineering (e.g., cost and performance improvements for product revisions, field support); and, project management.

Industry on Campus

One anecdote from an academic on the panel received universal acclaim from the audience.

“We had an executive visit campus from a high tech company. He met with students, and spent considerable time with them describing the kinds of microelectronics opportunities available and the skills the company was seeking. He talked about potential career paths, and the company’s focus on employee development. That made a huge impression on the students.”

Perhaps more industry professionals could reach out to universities. Contact the IEEE student chapter and offer to meet with students. Buy pizza. Share your own passion for microelectronics. Indicate to them that they would be working on the most complex systems ever conceived – “one trillion transistors” – using the most advanced manufacturing techniques – “atomic layer deposition”. And, their efforts could help the planet address critical issues we all face, from improving healthcare to enhancing transportation to enabling faster communications technology, all with a focus on power efficiency.

Follow-up

I would welcome your insights into ways to address the engineering shortage issue.

If you are involved in the American Semiconductor Academy initiative, either from SEMI or academia, please reach out with more info – I would like to better understand (and promote) the activities underway.

If you are a microelectronics student, why did you choose to pursue this field of study?

I am intrigued by the “tapeout experience” course offering, and how that could attract more microelectronics students – look for another article in the future.

Thanks in advance for your feedback.

-chipguy

Also read:

TSMC 2022 Technology Symposium Review – Advanced Packaging Development

TSMC 2022 Technology Symposium Review – Process Technology Development

Inverse Lithography Technology – A Status Update from TSMC

July 3, 2022July 6, 2022

Supply Chain Verification: Critical Enabler for Next-Generation Medtech Innovations

Supply Chain Verification: Critical Enabler for Next-Generation Medtech Innovations
by Bob Smith on 07-03-2022 at 6:00 am
Categories: Events

Chip design verification has long been a key component of any design project developing silicon intended to go into manufacturing. As designs become more complex, so does the manufacturing risk, and the focus on thorough verification becomes ever more critical.

Another dimension of complexity coming into play and considered throughout the entire electronic system. The shift toward chiplet-based design, 3D-IC and other innovative packaging technologies are driving the need for verification beyond the individual chip. System design verification that spans multiple devices, subsystems and even software code is becoming the norm for ensuring that an electronic system can be manufactured and perform as intended.

And yet, not all markets have the same requirements. Consider the differences between a low-cost consumer electronic product and an electronic medical system or device implanted in a human body. For example, the consumer product may have an expected lifetime of flow years and, if it malfunctions, it is annoying, but not life-threatening. Conversely, a medical electronic system may require an operating lifetime of more than 10 years and malfunctions are not tolerable as they may lead to serious health consequences, including death. In the case of both examples, rigorous verification is required. In the case of the medical electronic system, requirements for full system verification are much more stringent.

Yes, system design verification is more important now because of more use cases, applications and extended lifecycles. The requirement for functional verification runs through the entire electronic product design manufacturing supply chain. Without thorough verification, the supply chain can be compromised.

Given these scenarios, the ESD Alliance, a SEMI Technology Community, is drawing attention to the challenges and opportunities available throughout the entire electronic product design and manufacturing supply chain. It is sponsoring a panel discussion at SEMICON West on how supply chain verification is becoming a critical need in medical technology applications. “Supply chain verification” implies that thorough verification is required across the entire system of chips, components, and packaging. Our panel brings together experts in chip design, system design and verification, and advanced packaging technologies who will discuss supply chain verification challenges that must be undertaken in developing electronic medical devices and products where safety and reliability are the most important factors.

We invite you to join us for “Supply Chain Verification –– Critical Enabler for Next-Generation MedTech Innovations” Tuesday, July 12, 2022, 11:35 a.m. – 12: 25 p.m. in the Meet the Experts Stage, Moscone South, Exhibition Level, Room 2.

Our session moderator is Lucio Lanza of Lanza techVentures and our panelists are:

Mike Chin –– Intel

Lu Dai –– Qualcomm

Dave Kelf –– Breker Verification Systems

Jan Vardaman –– TechSearch International

Conference passes to both SEMICON West and the co-located Design Automation Conference can be used to attend this panel discussion.

The ESD Alliance will host a reception Wednesday, July 13, from 6 p.m. until 7:30 p.m. at Moscone Center South, Level 2, North Terrace. SEMICON West or DAC badges are required for entry.

SEMICON West 2022 Hybrid will be held July 12-14 at the Moscone Center in San Francisco. Registration is open. The Design Automation Conference (DAC), the premier gathering focused on the design and design automation of electronic circuits and systems, will be co-located with SEMICON West 2022 Hybrid. Registration is open.

About the ESD Alliance

The ESD Alliance, a SEMI Technology Community, serves as the central voice to communicate and promote the value of the semiconductor design ecosystem as a vital component of the global electronics industry. We have an ongoing series of networking and educational events, programs and initiatives. Additionally, as a SEMI Technology Community, ESD Alliance member companies can join SEMI at no extra cost. To learn more about the ESD Alliance, visit the ESD Alliance website. Or contact me at bsmith@semi.org if you have questions or need more information.

Engage with the ESD Alliance at:

Website: www.esd-alliance.org

ESD Alliance Bridging the Frontier blog

Twitter: @ESDAlliance

Facebook

Also read:

The Lines Are Blurring Between System and Silicon. You’re Not Ready.

Multiphysics, Multivariate Analysis: An Imperative for Today’s 3D-IC Designs

ASML EUV Update at SPIE

July 2, 2022March 26, 2023

Micron kicks off the down cycle – Chops 2023 capex – Holding inventory off street

Micron kicks off the down cycle – Chops 2023 capex – Holding inventory off street
by Robert Maire on 07-02-2022 at 10:00 am
Categories: Semiconductor Advisors, Semiconductor Services
2 Comments

-Micron reports weak outlook for fiscal Q4
-2023 capex to be down versus 2022 capex of $12B & Q3’s $2B
-Company keeping inventory off street to support pricing
-Memory is usually the first shoe to drop in a down cycle

Sharp drop in demand at end of Q3…..

Micron reported a sharp drop in demand at the end of its fiscal Q3, which is similar to what we have been hearing and what we reported in recent newsletters. This is a demand side driven imbalance as demand has fallen sharply in the face of supply growth remaining relatively steady. DRAM was 73% of revenues and prices for both DRAM and NAND declined in the quarter. Obviously the industry is bracing for a bit of a storm ahead in the fall.

Holding back inventory

Micron is holding inventory off the street in order to both shore up near term pricing as well as supplement next years product availability while it slows down production rates. This obviously is a strong implication that its current production ramp rate will slow significantly.

Capex was $12.5B in fiscal 2022 – could easily get cut in half

The capex run rate in the just reported Q3 was $2.5B in the quarter or an annual run rate of $10B. We would not at all be surprised to see next years capex cut down to half or less of 2022’s which could be in the range of $6B or $1.5B a quarter or less. The company indicated that its advanced process technology devices were ahead of schedule so they can easily take their foot off the spending gas and coast for a while.

Memory is usually the first to get whacked in a down cycle

We have been suggesting that memory is more consumer centric than other semiconductor parts and as such is more susceptible to declines in consumer spend which is what Micron management was calling out. So it should come as no real big surprise that Micron reported it first. Memory is obviously the ultimate commodity semiconductor product with little to no differentiation despite protests to the contrary.

Samsung will probably echo Micron

We would expect Samsung to repeat what Micron has said as they are in the exact same markets with the exact same products and can’t escape the weakness in demand and pricing. We would hope that Samsung follows Micron and holds product off market to stabilize pricing or things will get very ugly very fast. We would expect a similar slow down in memory capex spend at Samsung but larger in actual dollars as Samsung is a bigger player. Samsung’s spend for logic/foundry should hold up a little better but will likely slow as well

Intel’s warning in line with memory dive

Intel’s warning a few weeks ago was probably in the same timeframe that Micron saw business weaken, likely in similar end markets. We would certainly imagine that this relates to AMD as well. We would certainly be concerned about pricing in the processor market between Intel and AMD as that is already a bone of contention and the fight could worsen if the pie shrinks.

Bigger impact on Semiconductor Equipment

The second order derivative play is that when the chip companies catch a cold the equipment companies get pneumonia. In this case the poster child for memory makers is Lam, followed not too far behind by Applied. KLA is less vulnerable and ASML is more or less immune. Any litho scanners that Micron doesn’t take will likely be snapped up in foundry/logic (at least until that sector rolls over…)

CHIPS for America gets another nail in the coffin

Its a bit hard to argue that the semiconductor industry needs more capacity when demand is falling off and product is being held off the market. If Micron cuts its capex by half, its hard, if not embarrassing for them to hold out their hand for help from the government especially in light of stock buy backs they are doing. It would be a textbook example of “corporate welfare” and why the government shouldn’t help out. It would be throwing gasoline on the fire of excess supply in light of declining demand. While the case can still be made for “on shoring” of chip capacity the argument of shortages just went out the window.

The Stocks

Obviously Micron will get hit as will the broader SOX index especially among the semiconductor equipment companies who could see that declining capex directly. We don’t think this is in any way a Micron specific issue but at the very least a memory market issue that will likely spread. Earnings season could get very ugly indeed as more shoes could drop in the tech and chip sectors

About Semiconductor Advisors LLC
Semiconductor Advisors is an RIA (a Registered Investment Advisor), specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also read:

Semiconductor Hard or Soft Landing? CHIPS Act?

CHIPS for America DOA?

Has KLA lost its way?
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July 2, 2022March 26, 2023

Semiconductor Hard or Soft Landing? CHIPS Act?

Semiconductor Hard or Soft Landing? CHIPS Act?
by Robert Maire on 07-02-2022 at 6:00 am
Categories: Semiconductor Advisors, Semiconductor Services
6 Comments

-Chip cycle will come down. Only question is landing impact
-What does cyclical end do to re-shoring & build out plans?
-Is it less demand, excess supply or both? Does it matter?
-CHIP Act rescue efforts get desperate switching to threats

Any landing you can walk away from is a good one

For those of us who have been in the semiconductor industry long enough to live through multiple cycles, we know an end to a cycle is inevitable, the main question is how bad the down cycle is?

In the bad old days, down cycles were a disaster where most in the industry lost money and reduced staff and tried to ride it out.

More recently, down cycles have been more like benign pauses in an otherwise constant up cycle. Increasing and widening demand for chips has been cushioning short periods of excess supply and reduced demand.

In addition, the industry, primarily on the memory side, has been more rational and incremental in its capex spending and expansion plans which has moderated past over supply cycles.

Why is this cycle different from all other cycles?

1) We are coming off a cycle in which the lack of semiconductors did serious damage to other industries and got people’s attention. Previous chip cycles came and went and no one outside the industry was aware, let alone cared about the semiconductor industry – We got noticed in a negative way.

2) Everyone woke up to the realization of the concentration of production that is Taiwan and TSMC. It’s one of those things that just creeps up on you until its there and then its a big surprise. Customers finally got the memo that there is a giant single point of failure in a high failure risk geopolitical area. No one realized that the entire tech industry and a huge chunk of the global economy was based on an embattled island that most of the world doesn’t even recognize.

3) The supply chain became a major issue. Covid showed how both interconnected and vulnerable the global chip supply chain is. Having chips transit through 10 countries on their way to end users is no longer acceptable. People now care where their chips come from. Everybody now wants their own , independent chip fabs. Not because we need the capacity but because we need independence from the global supply chain. We want to keep things within out borders or at least minimize the exposure of the chain.

4) China got serious on being a player in semiconductors. China realized that it needs to become dominant in semiconductors to beat the US, not only economically but militarily and in intelligence related assets. China became the biggest CAPEX spender and fastest most aggressive semiconductor grower, not driven by economics but by global dominance aspirations which trumps and upsets rational economic drivers.

These four major differences will impact how the industry reacts as well the depth and length of any cycle. All four factors will likely cause the industry to spend much, much more on capex and building out new facilities than it really needs to just satisfy normal demand.

These four factors taken together suggest significantly excess spending in semiconductor capacity due to 1) economic risk 2) single point of failure risk 3) supply chain risk 4) strategic imperatives.

This is compared to more “normal” previous cycles where all the industry was trying to do was balance global supply and global demand.

We have the serious makings of a potential supply glut that the industry has never seen before

Demand is good but inflation and global risks will dampen overall growth

Demand for semiconductors has never been better or more widespread. Chips are in absolutely everything become as pervasive as the air we breath. Demand and new applications seems to grow by the day.

The problem is that macro economic issues, such as inflation and geopolitical issues like Ukraine seem likely to significantly slow the overall economy to the point where even semiconductors and tech in general slows from their torrid pace.

Aside from inflation fears we also have the potential of artificial restrictions specifically on the semiconductor industry like cutting Russia and China off from chip purchases that will artificially curb demand.

Is it weak demand or excess capacity or both that turns the cycle? It doesn’t matter

Like many other industries its not just supply and not just demand that make for health but rather the balance between the two. An imbalance in either direction is no good in the long run. Obviously its even worse when both are going in the wrong direction, increasing excess supply coupled with demand falling. Although we are not quite in the “double whammy” mode quite yet we see vectors pointing in the wrong direction.

Off a cliff without skid marks – No one ever sees it coming

Most all previous semiconductor cycles seem to be going along just fine until they aren’t. The surest sign seem to be inexperienced analysts and company management saying that the industry is no longer cyclical, run for the doors!

Just a few short years ago Samsung put the brakes on and virtually halted all CAPEX spend for a few quarters seemingly out of the blue. Semiconductor makers have become relatively fast at reacting to perceived changes. Intel spoke about years of short supply of chips until recently when it appeared to warn on demand. That was clearly a shock. The industry turns on the proverbial dime.

CHIPS Act desperation is starting to show

It seems quite clear that the CHIPS Act has now gone into desperation mode. You know that’s the case when everyone changes from what great benefits the Act will have to what a disaster things will be without it. Intel is threatening to cancel its groundbreaking in Ohio if the CHIPS Act doesn’t pass.

Pat Gelsinger on Ohio delay & CHIPS Act

US Commerce Secretary, Gina Raimondo said that a $5B Texas wafer fab, that will employ over 1000 people won’t happen if the CHIPS Act doesn’t pass.

Gina Raimondo CHIPS Act comments link

The Semiconductor Industry Association has also ramped up recent efforts to get the CHIPS Act passed.

Not everyone is on board with the CHIPS Act. Legislators seem to be raising more questions. The highly respected and regarded Robert Reich, who is bi-partisan and worked for Presidents Ford, Carter, Clinton and Obama has written a scathing rebuke of CHIPS for America as “corporate welfare”

Robert Reich CHIPS Act link

The problem we see is time is running out. We are a month away from summer congressional recess and after that we get into full blown election mode during which nothing of substance will get done.

January 6th has sucked most of the oxygen out of the room, including away from Ukraine and even inflation. Chips are so far down the list they are forgotten about. It would be a Hail Mary if the CHIPS Act gets passed at this point

The Stocks

Obviously the potential end of the cycle and reduced demand coupled with potentially excess supply is not a good thing.

The CHIPS Act which was likely more important for its investment tax credit than the paltry $10B a year in pork barrel aid doesn’t help matters and hurts the US specifically.

Obviously semiconductor equipment makers are on the end of the whip as usual. What’s bad for chip makers is usually way worse for chip equipment makers. No surprise here.

In terms of chip makers, we think TSMC remains the best positioned overall and in command of the entire industry. The second and third tier chip makers will suffer the most and have the most risk.

TSMC has the margin and ability to set pricing in the market such that its factories remain full while smaller less capable competitors who live under TSMC’s price umbrella will see their utilization fall and impact their earnings. Global Foundries that could only get to break even and profitability during the biggest chip shortage and associated demand is likely most at risk if demand weakens as customers go back to TSMC where they came from.

SMIC likely continues to do well even though they are second tier they have a captive audience in China.

Apple, Qualcomm, Broadcom, Nvidia, AMD and Intel will still depend on TSMC.
We think there could be significant downside potential on the memory side as memory tends to be a bit more consumer related.

We could see significant impact at both Samsung and Micron and have already heard about memory weakness in H2 2022.

The lack of the CHIPS Act could disadvantage US companies and projects and generally will weaken the US competitive positioning.

Its unclear if the CHIPS Act could be brought back to life after the fall election before the end of the year if it doesn’t get passed in the next 4 weeks. Its more likely that it will either go away entirely or get pushed deep into next year especially especially if there is a change in control of the legislative branch which will have bigger priorities.

Overall there seems to be a lot more near term downside than upside risk. The longer term certainly remains great but things could get even choppier in the next few quarters.

Also read:

CHIPS for America DOA?

Has KLA lost its way?

LRCX weak miss results and guide Supply chain worse than expected and longer to fix

Chip Enabler and Bottleneck ASML

Podcast EP92: The Impact of a Specification-Driven Correct-by-Construction Approach on Design and Verification with Agnisys

Podcast EP92: The Impact of a Specification-Driven Correct-by-Construction Approach on Design and Verification with Agnisys
by Daniel Nenni on 07-01-2022 at 10:00 am

Dan is joined by Anupam Bakshi, founder and CEO of Agnisys. Anupam has more than two decades of experience implementing a wide range of products and services in the high tech industry. Prior to forming Agnisys, he held various management and technical lead roles at companies such as Avid Technology Inc., PictureTel, Blackstone, Cadence and Gateway Design Automation.

Anupam discusses the Agnisys specification-driven development flow, in which users describe registers and sequences for system-on-chip (SoC) and intellectual property (IP) projects, and then automatically generate the RTL design and verification suite. The benefits of this approach and where it is applicable are discussed.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.